6862655b0d
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
71b5004b25
projects- drp moved to up-clock domain
2015-06-01 14:57:59 -04:00
4927ca85c2
projects- jesd-align port name change
2015-05-20 14:24:26 -04:00
e332fa01c8
ad6676evb, daq2, fmcadc2, fmcjesdadc1, usdrx1: Updated jesd reset connection
2015-04-30 12:11:46 +03:00
037484e1d0
usdrx1: Updated project to the latest framework
2015-03-25 17:39:51 +02:00
4ea86de4db
usdrx1_zc706: Update interrupts.
2014-11-27 14:03:54 +02:00
d1af4d2951
usdrx1_fmc: Fix GT lane number definition.
2014-11-27 14:03:10 +02:00
a0d27a117c
usdrx1: Updated project with new synchronization mechanism. Fixed timing constraints
2014-10-22 13:20:44 +03:00
17675863e0
all_projects: Fix the interrupt connections to preserve IRQ layout
2014-10-22 11:48:08 +03:00
8934a66013
usdrx1: Update project so that the AD9671 cores can be synchronized
2014-10-13 17:06:40 +03:00
296983707b
usdrx1: Updated project to 2014.2
2014-09-23 22:45:50 -04:00
5af2474d51
usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization
2014-09-23 22:44:33 -04:00
bdf01738a1
ultrasound: disconnected ADN4670 chips from SPI lines.
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Connected everything to ground so that the the clock selected is 0 and all outputs are enabled
2014-09-23 22:30:42 -04:00
d33fb07587
usdrx1: Modified the GPIO assignments so that board specific GPIOs start from GPIO 32.
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GPIOs for which the directions is known, have been specifically assigned.
The SPI clock has been changed to a lower frequency.
2014-09-16 15:56:19 -04:00
d4db53c3b0
usdrx1_spi: Modified module to be compatible with altera
2014-09-16 15:53:11 -04:00
50faf0c53a
Remove executable flags from non-exectuable files
2014-09-09 15:05:06 +02:00
a773cc4992
usdrx1: updated project
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ad_jesd_align wasa updated to be able to work with frames that have more than 4 octets per frame
2014-09-01 15:18:39 +03:00
6e444559b5
usdrx1: global clock fix
2014-06-10 18:09:49 +03:00
96541f0a7f
usdrx1: zc706 updated for usdrx1
2014-04-10 11:05:13 -04:00
6f36f74eea
usdrx1: common board files
2014-04-10 11:05:11 -04:00
ac1c145a61
usdrx1: initial checkin
2014-04-10 11:05:10 -04:00
Lars-Peter Clausen
Rejeesh Kutty
Adrian Costina
Istvan Csomortani