Commit Graph

25 Commits (03682f6193072e078b59ac724660d6633043c810)

Author SHA1 Message Date
Laszlo Nagy 51b643b978 Makefile: Fix misc makefiles from projects and library 2021-10-05 14:24:48 +03:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
LIacob106 16a93a804b adrv9001[intel]: Add second pair of DMAs
fix observations for PR
2021-09-01 15:04:14 +03:00
alin724 f8c82c611d axi_adrv9001: Add support for symbol operation mode on Xilinx devices
Add CMOS support for the interface for the following symbol modes on Xilinx devices:

A              B  C       D                     E       F      G            H
CSSI__1-lane   1  16/8    80(SDR)/160(DDR)      80      -      SDR/DDR      SDR/DDR->4/2(C=16), 2/1(C=8)

Columns description:
A - SSI Modes
B - Data Lanes Per Channel
C - Serialization factor Per data lane
D - Max data lane rate(MHz)
E - Max Clock rate (MHz)
F - Max Sample Rate for I/Q (MHz)
G - Data Type
H - DDS Rate

CSSI - CMOS Source Synchronous Interface
2021-08-17 15:33:06 +03:00
stefan.raus 1f24344620 Update Quartus version to 20.4
Update quartus compilation tools from 20.1 to 20.4.
Remove hardcoded version from axi_adrv9001 ip.
2021-08-12 11:15:01 +03:00
Josh Blum e1829a061d adrv9001: fixes for reset metastability on xilinx ioserdes
* fixes DRC warning that the clocking configuration may result in data errors
* fixes ioserdes reset issue with synchronous de-assert in data clock domain
2021-07-09 11:11:04 +03:00
Laszlo Nagy aa180fb272 axi_adrv9001: Let gate signals have initial value, useful for simulation 2021-05-26 15:44:45 +03:00
Laszlo Nagy b85784ebe8 axi_adrv9001: rx: calculate ramp value based on received value 2021-05-26 15:44:45 +03:00
Laszlo Nagy 9a93b56882 axi_adrv9001:rx: Add reset to link layer
Fix random valid signals after resets on the Rx interface.
2021-05-26 15:44:45 +03:00
Laszlo Nagy 4c35af74d4 axi_adrv9001:rx:phy: do not generate valid while in reset 2021-05-26 15:44:45 +03:00
Laszlo Nagy 32dbde6945 axi_adrv9001: Allow running Rx2/Tx2 channels in R1 mode without Rx1/Tx1
This commit removes the deadlock created while trying to use the Rx2/Tx2
channels without the Rx1/Tx1 channels enabled first.
2021-05-26 15:44:45 +03:00
Laszlo Nagy 08b0d19731 axi_adrv9001: Populate correct ratio of the SSI interface and user interface clocks
Depending on FPGA technology the physical layer uses different
deserialization factors and corresponding clock division factors to
divide the source synchronous interface clock. This must be
exposed to software so it can act on it while setting the DDS rate.

Xilinx CMOS clock ratio - 4
Xilinx LVDS clock ratio - 4
Intel  CMOS clock ratio - 1
2021-05-26 15:44:45 +03:00
Laszlo Nagy c718ba91f1 axi_adrv9001: Add status bit for Tx clocking
If Tx source synchronous clock is not routed through clock capable pins
the interface and driving logic must run on the Rx interface clock.
This introduces a dependency, Rx interface must be bring up before the
Tx. In this mode a Tx only operation is not possible.

This is done through a synthesis parameter.
Expose this parameter to the software so it can query if the limitations
exists in the implementation.
2021-03-17 16:34:12 +02:00
stefan.raus 4a772265a9 Update Quartus Prime version from 19.3.0 to 20.1.0
adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
2021-03-08 11:29:33 +02:00
Laszlo Nagy 85729def2a axi_adrv9001: Double sync control lines between interface 1 and 2 2021-03-04 11:13:10 +02:00
Laszlo Nagy 50c4c3e815 axi_adrv9001: Fix channel 3 for Tx1 in DMA mode 2021-03-04 11:13:10 +02:00
Laszlo Nagy 3aa8a631d0 axi_adrv9001: Quartus 19.3 updates 2021-03-04 11:13:10 +02:00
Laszlo Nagy 714d557245 axi_adrv9001: Add opt-in synthesis parameters 2021-01-26 15:22:41 +02:00
Laszlo Nagy 31929167d3 axi_adrv9001: Use global clocks for divided down clock 2021-01-26 15:22:41 +02:00
Laszlo Nagy c7046a6d72 axi_adrv9001:axi_adrv9001_rx_channel: fix ramp signal checking 2021-01-26 15:22:41 +02:00
Laszlo Nagy 54c2cf7d12 ad_tdd_control: Fix rx/tx only behavior
When tx_only disable rx_enable and vice-versa
2021-01-20 13:00:01 +02:00
Laszlo Nagy 58f2eec127 axi_adrv9001: Export TDD mode 2021-01-20 13:00:01 +02:00
Laszlo Nagy afa3f11206 axi_adrv9001: Add TDD support 2021-01-20 13:00:01 +02:00
Istvan Csomortani 37254358dd makefile: Regenerate make files 2020-10-20 12:51:10 +03:00
Laszlo Nagy 64f6762a05 library:axi_adrv9001: Initial version
ADRV9001 interfacing IP supports the following modes on Xilinx devices:

A              B  C       D       E       F      G        H
CSSI__1-lane   1  32      80      80      2.5    SDR      8
CSSI__1-lane   1  32      160     80      5      DDR      4
CSSI__4-lane   4  8       80      80      10     SDR      2
CSSI__4-lane   4  8       160     80      20     DDR      1
LSSI__1-lane   1  32      983.04  491.52  30.72  DDR      4
LSSI__2-lane   2  16      983.04  491.52  61.44  DDR      2

Columns description:
A - SSI Modes
B - Data Lanes Per Channel
C - Serialization factor Per data lane
D - Max data lane rate(MHz)
E - Max Clock rate (MHz)
F - Max Sample Rate for I/Q (MHz)
G - Data Type
H - DDS Rate

CSSI - CMOS Source Synchronous Interface
LSSI - LVDS Source Synchronous Interface

Intel devices supports only CSSI modes.
2020-08-24 17:49:12 +03:00