806947444f
ad9434_fmc: Port redeclaration as a wire is not allowed
2017-04-20 14:33:47 +03:00
1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
bc9483c5a2
Ip automatic version: Update ad*/common/ad*_bd.tcl
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ad6676evb/common/ad6676evb_bd.tcl
ad7616_sdz/common/ad7616_bd.tcl
ad7768evb/common/ad7768evb_bd.tcl
ad9265_fmc/common/ad9265_bd.tcl
ad9434_fmc/common/ad9434_bd.tcl
ad9467_fmc/common/ad9467_bd.tcl
ad9739a_fmc/common/ad9739a_fmc_bd.tcl
adrv9371x/common/adrv9371x_bd.tcl
adv7511/common/adv7511_bd.tcl
fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 18:52:37 +03:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
7ca8e10004
make: Update Make files
2016-08-01 14:24:48 +03:00
3006c5a223
make updates
2016-04-11 16:14:59 -04:00
977d9d0624
Merge branch 'hdl_2015_r2' into dev
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Conflicts:
projects/daq1/common/daq1_spi.v
2016-03-02 13:52:15 +02:00
40fb68dfd5
ad9265, ad9434, ad9467, daq1, daq2, daq3, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1, fmcomms6, fmcomms7, usdrx1: updated common spi module so that spi streaming is possible
2016-03-02 13:39:37 +02:00
ab99c4456a
ad9434_fmc: Delete unnecessary set_property call
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HPx interface is activated by the ad_mem_hpx_interconnect process
2016-01-14 15:41:23 +02:00
9d2b8809df
Makefiles: Updated Makefiles
2015-10-23 10:44:27 +03:00
e14e9294c5
project-names -- variables causes scripts to fail- too much parsing
2015-10-16 14:13:56 -04:00
960c711f3b
ad9434_fmc: Drop explicit axi_dmac clock synchronicity configuration
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The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:44 +02:00
d52308f074
axi_dmac: Change parameter name 2D_TRANSFER
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Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
57cfb7cfb1
hdl/library: Update the IP parameters
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The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
10a3ce96fe
ad9434_fmc: DMAC's destination clock must be more than or equal to adc_clk/4 (125 Mhz)
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DMAC's destination clock set to 200Mhz
2015-08-10 17:57:52 +03:00
a7da779b94
Makefile: Updated Makefiles
2015-07-16 18:19:42 +03:00
47469ad375
ad9434/ad9467 : Connect reset signal for AXI streaming interface of the device dma
2015-06-04 18:09:48 +03:00
f91fbf1bc1
ad9434_zc706: Fix SPI interface
2015-05-22 12:31:48 +03:00
a6cae6b477
iobuf: do is a system verilog keyword
2015-05-21 14:06:17 -04:00
6b9906b22b
Refresh Makefiles
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Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
c19749361d
Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
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Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
949abcdc8f
Makefile: Updated makefiles so that the project recipe does not depend on lib
2015-05-06 14:58:29 +03:00
dc2b37bd0c
Makefile: Added top level Makefile. Modified behavior of clean and clean-all
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Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.
The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
780455d68c
Makefile: Updated makefiles. Added makefiles for altera
2015-04-09 17:57:06 +03:00
5f8e9a74ea
makefile: updated
2015-04-07 16:32:01 -04:00
f79a152958
Makefiles: updated all makefiles adding clean functionality
2015-04-03 11:57:54 +03:00
544d4f579f
makefile: added
2015-04-01 16:28:30 -04:00
2fdc3d6d96
makefile: added
2015-04-01 16:28:29 -04:00
8443e94442
ad9434_fmc: Update project to the new framework
2015-03-23 13:00:50 +02:00
5e08e18022
ad9434_fmc: Update interrupts
2014-11-21 19:06:48 +02:00
3dbfa8cda6
ad9434_fmc: Fix PN monitor and device interrupt
2014-10-23 11:29:14 +03:00
8a4ab4e05a
projects/ad9434_fmc/common/ad9434_bd.tcl: Fix freeze - Design doesn't use SYNC
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Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-10-21 15:03:55 +02:00
7115864b4c
ad9434_fmc: Remove top level constraints
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Remove all the unnecessary top level constraint definitions.
2014-10-20 13:23:37 +03:00
0c56e5b912
ad9434_fmc: Fix GPIO width
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GPIO port width is 15 instead of 32
2014-10-20 10:59:30 +03:00
95842b8949
ad9434_fmc: Fix adc_valid signal path
2014-10-07 18:02:33 +03:00
115f33b8d6
ad9434_fmc: Fix pin constraints for ZC706
2014-10-07 17:58:29 +03:00
c1213ffe71
ad9434_fmc: Fix SPI interface
2014-10-07 17:51:14 +03:00
87c4c73e22
ad9434: Fix adc_clk constraint
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ADC clock is 500 Mhz.
2014-09-25 16:54:06 +03:00
82ed885b53
ad9434: Fix SPI line physical constraints
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SPI lines are not differential.
2014-09-25 16:53:16 +03:00
ccb0b135ca
ad9434: Fix the adc to dma interface.
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All the device2dma interfaces needs to have a generic form : (data, enable, valid)/channel
2014-09-25 16:50:09 +03:00
683561b67d
AD9434: Initial check in of the library and project with ZC706
2014-09-24 18:27:17 +03:00
Istvan Csomortani
AndreiGrozav
Adrian Costina
Rejeesh Kutty
István Csomortáni
Lars-Peter Clausen
Michael Hennerich