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26 Commits (040f72d17221e1dd2b17c375b50488acc66bc1be)

Author SHA1 Message Date
AndreiGrozav 9b2a106aa0 axi_jesd_gt: changed clock and reset naming to be consistent with the other projects 2016-03-15 11:20:31 +02:00
Rejeesh Kutty f3ffd5a63f up_gt: separate pll resets to tx/rx 2015-10-02 13:58:30 -04:00
Istvan Csomortani 57cfb7cfb1 hdl/library: Update the IP parameters 
The following IP parameters were renamed:

PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
 2015-08-19 14:11:47 +03:00
Rejeesh Kutty 3615c9cad7 axi_jesd_gt- bug fixes 2015-08-13 13:03:51 -04:00
Rejeesh Kutty 8697b0a8d6 axi_jesd_gt- ip script changes 2015-08-13 13:03:51 -04:00
Rejeesh Kutty 10d4da64dd axi_jesd_gt: move master/slave control to a util module 2015-08-13 13:03:51 -04:00
Rejeesh Kutty 3ed350efbc axi_jesd_gt- split up 2015-08-13 13:03:51 -04:00
Rejeesh Kutty 28e8275a5d library/axi_jesd_gt: split gt lanes 2015-06-12 15:56:03 -04:00
Rejeesh Kutty c6ebab7393 library- drp moved to up clock 2015-06-01 13:39:26 -04:00
Rejeesh Kutty 9762c65868 library- jesd-align port name change 2015-05-20 14:25:21 -04:00
Rejeesh Kutty e918588a4b library: remove axi-min-size parameter 2015-05-19 13:07:48 -04:00
Adrian Costina d623f77453 axi_jesd_gt: Added rx_jesd_rst and tx_jesd_rst. 
Resets for both up clock domain and rx clock domain are needed in some projects
 2015-04-30 12:07:36 +03:00
Adrian Costina a7a2d194e9 axi_jesd_gt: Switched rx_rst and rx_rst_done to up clock domain, to be compatible with xilinx JESD core 2015-04-28 15:04:18 +03:00
Rejeesh Kutty 9cdec38532 gt- report device type 2015-02-17 11:43:57 -05:00
Rejeesh Kutty fccadcec31 jesd_gt: lpm/dfe programmable 2015-02-13 11:33:25 -05:00
Rejeesh Kutty fd305f2eff es: added kcu105 gth 2014-11-17 09:55:09 -05:00
Istvan Csomortani f8e7796592 axi_jesd_gt: Fix lane number parameters 2014-11-12 17:43:32 +02:00
Rejeesh Kutty 64ec633438 gt: asymmetric no of lanes 2014-11-11 08:54:24 -05:00
Rejeesh Kutty 6f723ef9e5 axi_jesd_gt: lane mux on char qualifiers 2014-10-22 15:29:25 -04:00
Rejeesh Kutty 86724f7fc7 gt: tx lane interleaving 2014-10-15 14:51:00 -04:00
Rejeesh Kutty de33722470 up/constr: independent read/write and local constraints 2014-10-02 14:35:59 -04:00
acostina 5af2474d51 usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization 2014-09-23 22:44:33 -04:00
Lars-Peter Clausen 41cc92ef49 Remove BASEADDR/HIGHADDR parameters 
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-09-11 12:26:37 +02:00
Rejeesh Kutty cf56a568c6 kcu105: GTH updates 2014-06-05 14:27:38 -04:00
Rejeesh Kutty 916afd460f axi_jesd_gt: synchronization support 2014-05-19 14:17:31 -04:00
Rejeesh Kutty 80e5051894 axi_jesd_gt: initial checkin 2014-04-01 15:14:28 -04:00