11 Commits (046c89dacddef1ea619ed2d8971b1da154f834d5)

Author	SHA1	Message	Date
Lars-Peter Clausen	7be1f62b8b	ad9265_fmc: Drop explicit axi_dmac clock synchronicity configuration ... The axi_dmac core is now capable of detecting whether its different parts run in different clock domains or not. No need to configure it manually any more. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2015-09-18 15:27:25 +02:00
Adrian Costina	63aaa58861	ad9265_fmc: Updated project, removed ILA related clocks	2015-09-11 11:27:58 +03:00
Istvan Csomortani	d52308f074	axi_dmac: Change parameter name 2D_TRANSFER ... Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER	2015-08-20 10:14:22 +03:00
Istvan Csomortani	57cfb7cfb1	hdl/library: Update the IP parameters ... The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N	2015-08-19 14:11:47 +03:00
Adrian Costina	be6d6f627a	ad9265: Removed ILA	2015-06-08 15:03:34 +03:00
Adrian Costina	37bfb2ef4b	ad9265: Updated common, wfifo is reset by the adc_rst signal from axi_ad9265 core	2015-04-28 14:53:12 +03:00
Adrian Costina	a8b2292370	ad9265: Changed the dma clock	2015-04-02 22:27:55 +03:00
Adrian Costina	e7c33bc7d8	ad9265_fmc: Fixed spi connection. Changed ila clock to 200 MHz	2015-03-27 15:40:28 +02:00
Adrian Costina	58a5e0142c	ad9265_fmc: Updated project to the new flow	2015-03-24 10:37:06 +02:00
Adrian Costina	3c78d8fe58	ad9265_fmc: Added correct fifo to ILA. Updated interrupts	2014-10-31 14:49:29 +02:00
Adrian Costina	1d4bc47cea	ad9265: Initial commit	2014-09-23 22:51:42 -04:00