04843795d8
Merge branch 'hdl_2016_r2'
2017-07-20 11:42:47 +01:00
ed12efc620
arradio: Revert tcl related changes, to fix DDR Bandwidth related issue
2017-07-19 15:17:55 +03:00
128be6fb69
arradio: Changed clock domain of the ADC and DAC path to half the interface clock
2017-07-12 15:59:12 +03:00
f6f7cff8a0
util_clkdiv: Added altera version
2017-07-12 12:12:30 +03:00
1c1856140e
kc705: Fix ethernet address span
2017-06-30 14:20:39 +03:00
43a06950aa
axi_ad9361: Altera fix lvds interface
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- use internal serdes pll
2017-06-29 15:03:54 +03:00
cd29807edc
Revert "altera/ad_serdes: Fix net alignment for rx_out at ad_serdes_in"
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This reverts commit 0715c962f1
2017-06-29 09:25:04 +01:00
0761bc4f79
adrv9371_alt: Delete the fifos from the RX path
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+ Delete the rx_fifo and rx_os_fifo from the RX datapath
+ Change the receive DMA's source interface type to wr_fifo
2017-06-27 08:48:44 +01:00
8e2237b7ef
arradio: remove binary file
2017-06-23 17:46:25 +03:00
c21c6813a5
arradio c5soc: Update project to tcl flow.
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-Update to tcl flow
-Add missing i2c interface
2017-06-23 15:53:43 +03:00
3c49470e08
arradio/c5soc- qsys-script flow
2017-06-22 15:25:20 +03:00
2554677123
arradio/c5soc- remove qsys files
2017-06-21 17:40:37 +03:00
4ccaeffc8f
arradio/c5soc- updated to new framework/16.0
2017-06-21 17:39:55 +03:00
25a9949899
util_clkdiv: Register output port as a clock ( #33 )
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If the output pin is not defined as a clock, some of the Vivado IPI
propagation TCL will error out.
Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
2017-06-19 07:40:53 +01:00
105b9e7114
fmcadc5: Delete clock and reset duplicate connection
2017-06-14 11:33:11 +03:00
033737d6bf
adi_board.tcl: reset xilinx ip second commit
2017-06-09 19:16:19 +03:00
b14c3fb00d
Revert "adrv9371x- reset jesd ip using cpu clock"
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This reverts commit 9feeb72631
2017-06-09 19:12:36 +03:00
9feeb72631
adrv9371x- reset jesd ip using cpu clock
2017-06-08 10:49:37 -04:00
0b450a3dd7
adi_board.tcl: reset xilinx ip using cpu clock
2017-06-08 10:16:43 -04:00
ce90769cd8
pzsdr1: Fix IO definition for enable/en_agc
2017-06-06 16:44:04 +03:00
e99244b041
axi_ad9739a: Fix DDS set frequency
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- DDS out frequency was 4 times greater than the desired frequency
2017-05-10 17:30:15 +03:00
d3c6771ad6
axi_ad9371: Update dac_clk_ratio to 2
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DAC sampling frequency is two times of the JESD204
core clock.
2017-05-10 11:36:07 +03:00
e2ef470150
axi_ad9434: Fix input data rate
2017-05-04 16:38:21 +03:00
db459d96e9
daq2: zc706: Increase DAC FIFO size
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Currently the DAC FIFO size for the ZC706 DAQ2 project is 16kB. This is
quite a limiting size for practical applications. Increase the size to 1MB
to allow loading larger waveforms.
In this configuration the DAC FIFO will use half of the available BRAM
cells in the FPGA. This still leaves quite a few BRAMs available for
user application logic added to the design. If a user design should run out
of BRAMs nevertheless they can reduce the FIFO size, if not required by the
application, to free up some cells.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-28 11:34:45 +02:00
edefb9df44
axi_hdmi_tx: Fix assignment type
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The general rule of thumb is to use nonblocking assignments for
sequential always blocks.
2017-04-21 09:06:54 +03:00
54ff4d7bd0
ad_serdes_in: Fix generate block
2017-04-20 19:47:45 +03:00
7659700719
ad_serdes_clk: Fix generate block
2017-04-20 19:47:19 +03:00
03dcbc6a7d
ad_mmcm_drp: Fix generate block
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Can not be multiple 'if' statements inside a generate block. If there are
multiple cases use if/esle statement, but always should be one single
if/else inside a generate.
2017-04-20 19:43:46 +03:00
01165c926c
ad6676evb: Set default xcvr parameters to common design
2017-04-18 11:26:51 +03:00
ee398b4703
spi_engine: Fix CMD_FIFO_VALID generation
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Because of the memory map interface mux, up_waddr_s and up_wreq_s should be
used, when cmd_fifo_in_valid is generated.
2017-04-12 14:43:00 +02:00
7c191a089f
fmcjesdadc1: Update xcvr configuration to the default one used for this board
2017-04-12 14:41:43 +03:00
75409eeb38
util_fir_int: Shifted data so that the amplitude at the output of the filter is the same with the input
2017-04-12 13:49:53 +03:00
096aadbf91
util_fir_dec: Changed output rounding mode to Symmetric rounding to Zero
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This removes the added DC component that was introduced by the previous rounding mode
2017-04-12 13:49:37 +03:00
f7190dbbfd
adxcvr: Update Makefiles
2017-04-03 12:38:40 +03:00
fa5f81f6c6
axi_dacfifo: Fix clock for read address generation
2017-04-03 10:39:17 +03:00
7cb7bc111e
axi_dacfifo: Delete unused wires
2017-04-03 10:38:50 +03:00
14b4c4cf5f
axi_dacfifo: Define constraint for bypass
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The bypass module currently is supported, when the DMA data width
is equal with the DAC data width.
The dac_data output is enabled with dac_valid.
2017-04-03 10:38:28 +03:00
06605ed1e1
axi_dacfifo: Register the dac_valid signals
2017-04-03 10:38:09 +03:00
77081a6233
axi_dacfifo: Data from DMA is validated with dma_ready too
2017-04-03 10:37:45 +03:00
af3a4f5fc9
axi_dacfifo: axi_dvalid should come from dacfifo_rd module
2017-04-03 10:37:30 +03:00
b30041f7f3
axi_dacfifo: Redesign the bypass functionality
2017-04-03 10:37:08 +03:00
434d1ea52c
axi_dacfifo: Fix constraints
2017-04-03 10:36:46 +03:00
4bda798f13
Merge branch 'dev' into hdl_2016_r2
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Update the release branch with all the recent fixes.
2017-02-21 10:56:52 +02:00
040b61de60
fmcadc5: Updated default parameters
2017-02-20 17:13:58 +02:00
a15e05c497
adcfifo- remove axi-byte-width parameter
2017-02-17 15:29:10 -05:00
cb3d1883bc
fmcjesdadc1/a5gt- hard placement of ddr hr/qr registers
2017-02-17 15:21:33 -05:00
981a61bf16
axi_dacfifo: Clean up the axi_dacfifo_wr.v module
2017-02-17 18:40:02 +02:00
3e5054247b
scripts: For altera projects, when it doesn't meet timing rename the generated sof
2017-02-17 11:08:50 +02:00
e8bcbb74da
scripts: fixed tcl syntax for altera projects not meeting timing
2017-02-16 21:21:51 +02:00
f10866e4c3
axi_*fifo: Delete/replace AXI_BYTE_WIDTH parameter
2017-02-16 19:54:41 +02:00
Istvan Csomortani
Adrian Costina
AndreiGrozav
Rejeesh Kutty
Matthew Fornero
Lars-Peter Clausen