Commit Graph

3008 Commits (04a694251e62a328ddf4857739881ca29722e7a9)

Author SHA1 Message Date
sergiu arpadi 7cc5716ea8 ad469x: Remove sysid custom string init 2020-10-28 11:31:50 +02:00
sergiu arpadi 5359d991b2 ad469x_zed: Update bd.tcl with new port names 2020-10-28 11:31:50 +02:00
Istvan Csomortani ad4adddbe5 ad469x_fmc: Minor cosmetic update on the config file 2020-10-27 10:09:50 +02:00
Adrian Costina 0644edb389 fmcomms8: a10soc: Move RX and Observation to second SDRAM interface
This is an attempt to get full bandwidth without a FIFO
2020-10-26 18:12:14 +02:00
Adrian Costina 3a5097875f common: a10soc: Allow for the second SDRAM interface to be used at a different clock 2020-10-26 18:12:14 +02:00
Adrian Costina 6621fbec61 fmcomms8: a10soc: Initial commit 2020-10-26 18:12:14 +02:00
sergiu arpadi 35e4eb6a7b ad469x: Add reference design for ad469x eval board 2020-10-22 19:17:10 +03:00
Adrian Costina 83cebe899f daq3: Update projects to the new TPL
Also modified the FIFO ports to have the same widths so that in a
future commit the bypass would be available for cases when the
sampling rate won't be the maximum rate or the number of channels
active will be less than maximum number of channels
2020-10-21 18:59:37 +03:00
Istvan Csomortani 9f58b465ea adaq7980: Add AXI pulse generator to generate the offload trigger 2020-10-21 09:59:26 +03:00
Istvan Csomortani 37254358dd makefile: Regenerate make files 2020-10-20 12:51:10 +03:00
Sergiu Arpadi 1f6bba0aa1 ad77681: Add axi_clkgen ip for spi engine
spi_clk changed from 40MHz to 80MHz
2020-10-19 10:42:21 +03:00
Istvan Csomortani d6b23d5149 scripts/adi_pd_intel: Delete noisy print outs 2020-10-17 08:02:33 +03:00
Istvan Csomortani 66672932d5 adv7513/de10nano: Fix connection of ltc2308 SPI's interface 2020-10-14 10:37:14 +03:00
Sergiu Arpadi 72635d73e3 cn0540: Add axi_clkgen to Makefile 2020-10-14 00:05:57 +03:00
Adrian Costina 9364c8501a adrv9009_zu11eg: Add synchronization at application layer
Switch RX path reset to be controlled by the TPL and use
RX SYSREF as external synchronization for the ADC TPL
Use TX SYSREF for synchornizing the TX DDS
2020-10-07 09:04:21 +03:00
Laszlo Nagy 4026eaa19b ad9081_fmca_ebz: Fix device clocks termination
The device clocks are AC coupled LVDS lines without external termination.
For proper operation internal differential termination must be enabled,
the DQS_BIAS will DC bias the AC coupled signal to VCCO/2 (1.8/2) 0.9V
2020-10-06 16:13:21 +03:00
hotoleanudan 1c208c01d6
ad9656:Add reference design for the ad9656 eval board (#494)
Added reference design for the ad9656 evaluation board coupled with the
zcu102 carrier board. The JESD204 communication link that transfers data
from the 4 ADCs to the FPGA has the following paramenters : L=4, M=4, S=1,
F=2, HD=0, N=16, NP=16. The JESD204 line rate is configured to be 2.5GHz.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2020-10-06 09:53:40 +03:00
sergiu arpadi 23cd6d2f91 sysid: Remove cstring init string
These two projects were originally missed by the find/replace command
2020-10-02 23:34:40 +03:00
Sergiu Cuciurean da6d9da4f0 projects: cn0540: coraz7s: Add XADC support
The coraz7s has an Arduino/chipKIT Shield connector with 6 Single-ended
and 8 Differential Analog inputs tied to Xilinx's XADC.
The CN0540 uses the A0-5 pins as single-ended ADC channels to monitor
the differential input, ADC driver, and buffer voltages.

Signed-off-by: Sergiu Cuciurean <sergiu.cuciurean@analog.com>
2020-10-02 11:14:21 +03:00
Istvan Csomortani 11822e2824 cn0540/coraz7s: Set and input delay of one spi_clk cycle for the MISO line
Note, the current SCLK to spi_clk ratio is four. That means, the input
delay in the MISO line is 25% of the SCLK period.

If the SCLK to spi_clk ratio is changing, this constraint must be
updated.
2020-10-02 10:50:06 +03:00
Istvan Csomortani dae1de0405 cn0540/bd: Generate a 80MHz spi_clk
Generate a higher frequency of spi_clk using an axi_clkgen. (MMCM)

CAUTION: ad7768-1 is still violating the standard SPI timing,
reducing the timing window significantly for the last bit (or last high
bit).
2020-10-02 10:50:06 +03:00
Sergiu Arpadi c656a2e29b sysid: Initialize parameter 2020-09-30 19:12:24 +03:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Sergiu Arpadi bd2126fd2f cn0363: Remove iobuf for spi sdo
iobuf was generating drc warning because it was not fully connected.
2020-09-25 16:40:41 +03:00
Istvan Csomortani 9c827d6b03 cn0540/de10nano: Ignore 15003 critical warning
Ignore the following critical warning on DMAC instance:

Critical Warning (15003):  "mixed_port_feed_through_mode" parameter of RAM atom
system_bd:i_system_bd|axi_dmac:axi_dmac_0|axi_dmac_transfer:i_transfer| \
dmac_request_arb:i_request_arb|dmac_dest_mm_axi:i_dest_dma_mm| \
altsyncram:bl_mem_rtl_0|altsyncram_0tp1:auto_generated|ram_block1a1
cannot have value "old" when different read and write clocks are used.
2020-09-25 12:56:53 +03:00
Istvan Csomortani 9cac38017b daq2/a10soc: Set optimization mode to high performance effort 2020-09-25 12:56:14 +03:00
Istvan Csomortani 230c579339 common/s10soc: Input ports do not have a current strength property 2020-09-25 12:56:14 +03:00
Istvan Csomortani 5644907f75 adi_intel_msg: Dissable "unused TX/RX channel" critical warning for Stratix 10 2020-09-25 12:56:14 +03:00
Stanca Pop a738879fa0 ad77681evb: Remove redundant ad_data_clk 2020-09-25 12:20:41 +03:00
Adrian Costina 144fcc2965 adrv9009: Fix typo for number of samples calculation for observation channel 2020-09-25 11:58:58 +03:00
Adrian Costina bde2d1d66d fmcomms8: zcu102: Leave the SPI constraint at 25 MHz 2020-09-25 11:54:12 +03:00
Adrian Costina 4d2e05d5dd fmcomms8: common: In the SPI module, use ad_iobuf instead of a Xilinx primitive 2020-09-25 11:54:12 +03:00
Adrian Costina f8c2eb12d4 fmcomms8: zcu102: Remove the test pins, as they are not connected 2020-09-25 11:54:12 +03:00
stefan.raus 1e31b9dd97 arradio: Remove unused signals
Remove 'ad9361_clk_out' since is not used anymore, fixing in this way 'Warning (21074): Design contains 1 input pin that do not drive logic'
2020-09-23 09:16:48 +03:00
sergiu arpadi f2f6422751 sysid: Fix board/project name underscore issue 2020-09-17 10:32:58 +03:00
AndreiGrozav 6ae822d42c cn0506_rmii: Fix no defined clock warnings 2020-09-16 10:57:15 +03:00
Istvan Csomortani 49d4286459 cn0540/de10nano: Delete GPIO connection to DRDY 2020-09-15 18:14:23 +03:00
Istvan Csomortani 4838ac0ac2 cn0540/coraz7s: Time the SPI interface of AD7768-1 2020-09-15 18:14:23 +03:00
AndreiGrozav 0933949ad7 adv7513: Add initial project for de10nano 2020-09-15 18:14:23 +03:00
Stanca Pop 043ddbaf9f cn0540: Add de10nano reference design 2020-09-15 18:14:23 +03:00
Istvan Csomortani ad8d2d225f de10: Delete redundant base design 2020-09-15 18:14:23 +03:00
Stanca.Pop fd1c3c7cdd common/de10nano: Add de10nano base design 2020-09-15 18:14:23 +03:00
Stanca Pop 6cea8ce777 adi_project_intel: Add de10nano support 2020-09-15 18:14:23 +03:00
Istvan Csomortani 40772a8b2c ad40xx_fmc/zed: Fix constraints, to avoid critical warnings in synthesis 2020-09-15 13:08:39 +03:00
Sergiu Arpadi 3241924d14 sysid_intel: Added sysid to intel projects 2020-09-11 15:46:06 +03:00
Sergiu Arpadi f57643b451 sysid_intel: Added adi_pd_intel.tcl 2020-09-11 15:46:06 +03:00
AndreiGrozav 0152b645a6 m2k: Fix Warnings
Fix warnings caused by attempting to set a value to a disabled parameter.
2020-09-11 10:23:26 +03:00
Istvan Csomortani 9ee0f09078 daq3:qsys: Activate input pipeline stage for AD9680's JESD interface 2020-09-09 14:15:37 +03:00
Dragos Bogdan c8e0a1ec04 projects: adrv9009: intel: Update JESD204 LANE_RATE and REFCLK_FREQUENCY
To match the Linux default setup.

Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
2020-09-09 14:15:37 +03:00
Istvan Csomortani 61ece1f1e9 s10soc: Insert an additional bridge between DMA and HPS
Due to the interface differences between HPS's AXI4 and DMA's AXI4, the
tool will try to automaticaly add some bridges between the two
interface. Unfortunatly it does generate timing issues at the f2sdram0
interface of the HPS instance. By explicitly instantiating an AXI
bridge, these timing issues disappears.
2020-09-09 14:15:37 +03:00