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Author SHA1 Message Date
Istvan Csomortani a66029aef3 adrv9009/a10gx: Delete redundant timing constraints 2020-08-11 10:14:18 +03:00
Istvan Csomortani 02ada3bbf7 a10gx: Delete input/output delay definitions 
All input and output delays should be referenced to a virtual clock.

If the input and output delays reference base clocks or PLL clocks rather than
virtual clocks, the intra- and inter-clock transfer clock uncertainties,
determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports.
See mnl_timequest_cookbook.pdf for more info.
 2020-08-11 10:14:18 +03:00
Adrian Costina 401395cdd1 adrv9009: A10GX: Initial commit 2018-11-27 15:31:21 +02:00