c8e0a1ec04
projects: adrv9009: intel: Update JESD204 LANE_RATE and REFCLK_FREQUENCY
...
To match the Linux default setup.
Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
2020-09-09 14:15:37 +03:00
46b6bf8f8a
adrv9009/qsys: input pipline active for jesd204_rx and jesd204_rx_os
2020-09-09 14:15:37 +03:00
eb8e1142cd
adrv9009/intel: Fix the register address layout
...
The reconfiguration interface for the Stratix10 XCVR has a different
address width. Prepare the register map layout of the project to support
this new architecture.
2020-09-09 14:15:37 +03:00
8818089015
a10soc: Reconfiguration interface address width improvement
...
The reconfiguration interface's address width is different in various
architectures. Define the required address width in system_qsys.tcl.
2020-09-09 14:15:37 +03:00
71d500bdd4
adrv9009/intel: Use generic TPL cores
2020-05-26 16:22:30 +03:00
c930395773
adrv9009:qsys: use bundled AXIS interface
2019-05-16 13:27:19 +03:00
3183fbf226
adrv9009: update adcfifo/dacfifo
2019-01-23 14:45:45 +02:00
e09f3290ff
adrv9009: Move intel project to upack2/cpack2
2018-12-03 12:23:24 +00:00
e4048c7b04
adrv9009: A10SOC: Add second observation channel
2018-11-27 15:31:21 +02:00
f12bd3d246
adrv9009: A10SOC: Initial commit
2018-11-27 15:31:21 +02:00
Dragos Bogdan
Istvan Csomortani
Laszlo Nagy
Adrian Costina