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4959 Commits (04af519af87dcf293fb0bd14131738425a552c18)

Author SHA1 Message Date
Istvan Csomortani 04af519af8 axi_adxcvr: Re-indent ports 2019-03-21 14:30:39 +02:00
Istvan Csomortani 845c369c6b axi_adcvr: Add initial value for reg port definition 2019-03-21 14:30:39 +02:00
Istvan Csomortani 8996044978 axi_adxcvr: Fix warning related to up_es_reset 
Fix the following warning:

WARNING: [Synth 8-2611] redeclaration of ANSI port up_es_reset is not allowed

Also make sure, that in all configurations, the register has a diver.
 2019-03-21 14:30:39 +02:00
Istvan Csomortani 59713f96ab util_tdd_sync: Fix util_pulse_gen instantiation 2019-03-21 07:28:18 +00:00
Istvan Csomortani a337774dfa ad_ip_jesd204_tpl_dac: Add 8 bit resolution support 2019-03-20 15:51:28 +02:00
Istvan Csomortani e3e96177c4 ad_ip_jesd204_tpl_adc: Add 8 bit resolution support 
Add support for 8 bit resolution for the transport layer.

Fix parameter BITS_PER_SAMPLES propagation to all the internal modules, in
several cases this variable was hard coded to 16.
 2019-03-20 15:51:28 +02:00
Istvan Csomortani ac4d78b95d ad_datafmt: Add support for 8 bit data width 2019-03-20 15:51:28 +02:00
sarpadi 2f68c546f1
Merge pull request #244 from analogdevicesinc/axi_i2s_adi_update 
axi_i2s_adi: fixed xdc
 2019-03-20 13:42:23 +02:00
sarpadi 470f8cd33b
Merge pull request #245 from analogdevicesinc/dev_axi_pulse_gen 
AXI_PULSE_GEN
 2019-03-20 10:27:26 +02:00
Istvan Csomortani 0e7b38ebcf axi_pulse_gen: Initial commit 
The axi_pulse_gen is a generic PWM generator, which can be configured
through an AXI Memory Mapped interface.

The current register map look like follows:

  0x00 - VERSION
  0x04 - ID
  0x08 - SCRATCH
  0x0C - IDENTIFICATION - 0x504c5347 which stands for 'PLSG' in ASCII
  0x10 - CONFIGURATION - contains reset and load bits
  0x14 - PULSE_PERIOD
  0x18 - PULSE_WIDTH

Also update all the other modules, which instantiate the util_pulse_gen.
 2019-03-20 08:21:22 +00:00
Istvan Csomortani f15ed8475e util_pulse_gen: Change the counter to a down-counter 
To prevent the case, when after an invalid configuration, the generated
output PWM signal is constant HIGH, change the counter to a
down-counter. In this way the pulse will be placed at the end of the
PWM period, and if the configured width value is higher than the
configured period the output signal will be constant LOW.
 2019-03-20 08:21:08 +00:00
Istvan Csomortani 2d7b189ba3 util_pulse_gen: Add an input configuration port for pulse width attribute 2019-03-19 16:33:10 +00:00
Sergiu.Arpadi 0e333bf5ae axi_i2s_adi: fixed xdc 
ip now sets the xdc to late so that the timing constraints are set in the correct context
 2019-03-18 13:58:28 +00:00
Laszlo Nagy 8885caab13 scripts/adi_board.tcl: fix HP address mappings for ZynqMP 
In the current form, when connecting a master to the HP ports all
available slave address spaces are mapped to the master (DDR_*, PCIE*, OCM,
QSPI)

Let the PL masters have access only to the DDR_LOW and DDR_HIGH address
spaces to avoid unnecessary resource usage and increase timing margin.
 2019-02-27 15:04:41 +02:00
Laszlo Nagy a3ce8c5ca6 axi_rd_wr_combiner: Add rlast to the AXI MM interface 
The DMAC is relying on the rlast signal that marks the end of a burst.
 2019-02-21 17:09:53 +02:00
Laszlo Nagy c10c4d4f5e up_dac_common: fix address decoding 
Patch the typo introduced in a previous commit while attempting the
address space reduction.
 2019-02-19 15:38:45 +02:00
AndreiGrozav 1c8172de7f axi_adc_trigger: Cosmetic update 
Use localparam DW = 15 - SIGN_BITS
 2019-02-18 13:39:24 +02:00
AndreiGrozav 44e20d095c axi_adc_trigger: Fix triggering jitter effect 2019-02-18 13:39:24 +02:00
Adrian Costina 6e9bc398c3 fmcomms5: Connect overflow pin between adc_pack and adc_fifo 2019-02-14 14:36:45 +00:00
AndreiGrozav 2ec578c216 axi_hdmi_tx: Update file sources for Intel designs 2019-02-12 10:43:46 +02:00
AndreiGrozav ce04f46b80 motcon2_zed: Fix timing problems 
-change implementation strategy
-axi_dmac add extra registers AXI_SLICE_SRC

This was done to increase the overall timing margin.
 2019-02-12 10:43:46 +02:00
AndreiGrozav 2d825d8b7c daq3_zc706: Change implementation strategy 2019-02-12 10:43:46 +02:00
AndreiGrozav fae4d478d4 ad_csc: Generalize for CrYCB 2 RGB conversion 2019-02-12 10:43:46 +02:00
AndreiGrozav 74eacc2369 ad_csc(RGB2CrYCb): use signed multiplication. 2019-02-12 10:43:46 +02:00
AndreiGrozav 265781f29a axi_hdmi: Let the tools assign the csc resources 
Write code to pipeline data path for better DSP utilization on the
color space conversion.
In the old method the addition operations were performed outside the
DSPs
 2019-02-12 10:43:46 +02:00
Adrian Costina 47f7894881 util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4) 2019-02-11 17:20:08 +02:00
Laszlo Nagy ca1ba6a6fe axi_ad9144/axi_ad9152: patch up_tpl_common dependency 2019-02-01 08:28:28 +00:00
Istvan Csomortani b2d86bab47 util_axis_fifo: Fix the FIFO level generation in ASYNC mode 
The FIFO functions in 'first fall through' mode, adjust the fifo level
generation so it take into account the valid data which sits on the bus,
waiting for ready, too.
 2019-01-29 11:38:28 +02:00
Laszlo Nagy b221718bfe jesd204:up_tpl_common: reduce and move address space 
Limit the tpl register space to 128 locations mapped to 128-255 in the COMMON_ID segment.
 2019-01-23 17:44:33 +02:00
Laszlo Nagy 93df754800 up_adc_common/up_dac_common: reduce address space to half 
Limit the adc/dac common space to 128 registers mapped 0-127 in the COMMON_ID segment.
 2019-01-23 17:44:33 +02:00
Laszlo Nagy cf593d5a40 jesd204_tpl: addresses cleanup 
The TPL has an address space of 12 bits while the legacy subcomponents
have 16 bits. Update the module for a better readability.
 2019-01-23 17:44:33 +02:00
Laszlo Nagy 560e9b9e52 jesd204_tpl: expose jesd parameters to software 
This change will allow software to identify the available JESD framer/deframer
settings from the transport layer.
 2019-01-23 17:44:33 +02:00
Laszlo Nagy c37b24d00f fmcadc5: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy 4ec1204767 fmcadc4: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy 51e35e081f fmcadc2: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy 27f1e4eaed daq3: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy 9b048f1a0e daq2: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy b98eb28dca adrv9371: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy 3183fbf226 adrv9009: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy bed5ce516c adcfifo/dacfifo: fix alignments 2019-01-23 14:45:45 +02:00
Laszlo Nagy a3766b464b adcfifo/dacfifo: Use proc to create infrastructure 
Create the dacfifo/adcfifo infrastructure with procedures.
This will allow moving the parameters of the dac/adcfifo inside
the block design so it can be calculated based on other parameters.
 2019-01-23 14:45:45 +02:00
Laszlo Nagy c6c825c90a jesd204/tb: support for ModelSim and Xsim 
Adding support for ModelSim and Vivado Xsim.

Usage:
  export SIMULATOR=modelsim
    or
  export SIMULATOR=xsim
 2019-01-21 10:33:30 +02:00
Adrian Costina b052e40637 ad_ip_jesd204_tpl: Fix chanmax reporting for both ADC and DAC 2019-01-16 11:40:17 +02:00
Laszlo Nagy e864786d3a adrv9371: use generic TPL 
Use the generic TPLs for a better scalability to ease lane number
reductions.
 2019-01-14 17:21:00 +02:00
Laszlo Nagy 0b66b39352 adrv9009/zc706: make SPI selection consistent 2018-12-21 17:32:48 +02:00
Laszlo Nagy 3d7a376f8b Makefile: update makefiles 2018-12-21 17:32:48 +02:00
Laszlo Nagy c9f1c92eaa adrv9009: use generic TPL 
Make the block design parametrizable.
Limitations:
  F = 1,2,4
 2018-12-21 17:32:48 +02:00
Laszlo Nagy a65bafb056 ad_ip_jesd204_tpl_dac: expose OCTETS_PER_BEAT parameter 2018-12-21 17:32:48 +02:00
Laszlo Nagy 47093775ae adrv9009/zc706: top level cleanup 2018-12-21 17:32:48 +02:00
Laszlo Nagy 8adc285eab adrv9009/zc706: fix location constraints 2018-12-21 17:32:48 +02:00