04ce10a570
cosmetics: Change Altera to Intel in comments
2019-06-29 06:53:51 +03:00
2f0dbe6151
intel_mem_asym: Rename the alt_mem_asym to intel_mem_asym
2019-06-29 06:53:51 +03:00
1e074726db
intel_serde: Rename alt_serdes to intel_serdes
2019-06-29 06:53:51 +03:00
b0fbe1bb57
util_clkdiv: Seperate the IP source into an intel and xilinx version
2019-06-29 06:53:51 +03:00
84bd50d437
alt_ifconv: Remove unused IP
2019-06-29 06:53:51 +03:00
d5e5fcf17a
alt_mul: Remove unused IP
2019-06-29 06:53:51 +03:00
5329458a62
library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl
2019-06-29 06:53:51 +03:00
363494ab9c
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl
2019-06-29 06:53:51 +03:00
6e6f1347d7
project/scripts: Rename adi_project_alt.tcl to adi_project_intel.tcl
2019-06-29 06:53:51 +03:00
a589753d92
project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
2019-06-29 06:53:51 +03:00
43725429ac
adi_project: Rename the process adi_project_xilinx to adi_project
2019-06-29 06:53:51 +03:00
ec67a381e4
adi_project: Rename the process adi_project_altera to adi_project
2019-06-29 06:53:51 +03:00
79b6ba29ce
all: Rename altera to intel
2019-06-29 06:53:51 +03:00
d79fa179a3
spi_engine: Fix sync_bit instances
2019-06-28 11:18:29 +03:00
ba4a915af0
ad40xx/zed: fixed system_bd
...
spi_engine_execution: fixed sdo default
2019-06-28 11:18:29 +03:00
42b14f341a
axi_spi_engine: Generate false paths only on ASYNC_CLK mode
2019-06-28 11:18:29 +03:00
f4de1fecdc
spi_engine_execution: Add an additional register stage for the physical SPI
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The main reason is to improve timing when the SPI clock is more than
50 MHz. (the SPI Engine's spi_clk is more than 100MHz)
2019-06-28 11:18:29 +03:00
cf9d0814d5
ad40xx/zed: Place all the SPI registers near IOB
2019-06-28 11:18:29 +03:00
77ffa1f8ac
util_dec256sinc24b: Fix the accumulator
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Do a similar fix as for the decimation stage. (ab2788)
2019-06-28 11:18:29 +03:00
10e1abc22f
ad40xx_fmc/zed: Delete IOB TRUE constraints
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Vivado can not apply the IOB TRUE constraint to only one bit of a
registers. So these constraints will generate several CRITICAL WARNING.
Taking into consideration the maximum used frequencies and current
architecture these constraints are not critical.
2019-06-28 11:18:29 +03:00
158b018f58
spi_execution: Improve timing by defining resets for the shift registers
2019-06-28 11:18:29 +03:00
d802ece39e
spi_engine: Reindent execution module source code
2019-06-28 11:18:29 +03:00
6b110b6fb8
ad5758_sdz/zed: system constraint file cleanup
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removed redundant PACKAGE_PIN properties
2019-06-28 11:18:29 +03:00
0f2a1e7602
ad5758_sdz: Initial commit
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Initial version of AD5758 SDZ evaluation board support on ZedBoard.
No critical warnings in the Vivado log.
Bitstream generation passing.
Bring-up on actual board not done.
2019-06-28 11:18:29 +03:00
9ab88f1200
ad40xx: Initial commit
2019-06-28 11:18:29 +03:00
94f8d1b424
util_axis_upscale: Sign extension must be done separately for each channel
2019-06-28 11:18:29 +03:00
5f8269da03
spi_egine: Add a new register for dynamic transfer length configuration
2019-06-28 11:18:29 +03:00
40fbb37d6f
spi_engine: Add additional synchronization FIFO's to axi_spi_engine
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Add additional synchronization FIFOs to several interfaces of the
axi_spi_engine module, to prevent metastability and timing issues in
case when the system clock and the SPI clock are asynchronous.
2019-06-28 11:18:29 +03:00
91801bfe0d
spi_engine: Update the ad_rst instance
2019-06-28 11:18:29 +03:00
68c1f92066
spi_engine: Add a CDC fifo for the SYNC interface too
2019-06-28 11:18:29 +03:00
a19f6197cc
spi_engine: Fix indentation of axi_spi_engine.v
2019-06-28 11:18:29 +03:00
b81c8373e5
spi_engine: In read only mode SDO line should stay in its default level
2019-06-28 11:18:29 +03:00
85bbf95c57
spi_engine/offload: SDI_READY should be asserted while offload is inactive
2019-06-28 11:18:29 +03:00
746f457ef9
spi_engine: Software reset should reset the offload control registers too
2019-06-28 11:18:29 +03:00
19655b8092
spi_engine: Define SDO default state
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There are devices where the SDO default state, between transactions, is
not GND, rather VCC.
Define a parameter, which can be used to set the default state of the
SDO line.
2019-06-28 11:18:29 +03:00
45a08a004d
spi_engine:execution: Set default SDI driver value for all ports
2019-06-28 11:18:29 +03:00
8fb6fb329e
util_dec256sinc24b: Fix the differentiator
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Move the subtraction outside of the always block. In this way we're not adding
an additional delay element on to the output of the differentiator,
which brakes the transfer function of the filter.
2019-06-28 11:18:29 +03:00
b46a28d42f
adum7701: Delete redundant interrupt port in system_top
2019-06-28 11:18:29 +03:00
a15afa6c03
util_dec256sinc24b: Avoid generated clock from logic
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Do not use word_clk, create a clock enable signal instead.
2019-06-28 11:18:29 +03:00
59ce663479
util_dec256sinc24b: Fix resets
2019-06-28 11:18:29 +03:00
6668accc96
ad7405 : Initial commit
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This project is an inital version of the ADuM7701 (CMOS) or AD7405 (LVDS)
reference board.
2019-06-28 11:18:29 +03:00
554feaa1af
util_pulse_gen: Update ports for all outdated instance
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The new version of util_pulse_gen has different ports and port names.
Update all the instance:
- AD738x_FMC
- AD7768EVB
- ADAQ7980_SDZ
2019-06-28 11:18:29 +03:00
7fa620d253
gtm_projects: Update system_top
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In the latest system_top file we are not bringing out all the interrupt
signals from the block design. Delete all interrupt ports from the
system_wrapper instance.
Following projects were changed:
- AD5766_SDZ
- AD7134_FMC
- AD7616_SDZ
- AD77681EVB
- AD7768EVB
- ADAQ7980
2019-06-28 11:18:29 +03:00
21ce53f765
Revert "Move GTM projects to gtm_projects branch"
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This reverts commit 171093eca4
2019-06-28 11:18:29 +03:00
f22f448d4b
daq3:vcu118: Delete constraint related to smart connect
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Apparently this constraint will cause more harm than good. The tool will
try to prevent an invalid hold violation by increasing the net delay,
causing a setup violation on the same path. (inside the smart connect)
See more info here:
https://forums.xilinx.com/t5/AXI-Infrastructure/Smartconnect-and-Synchronous-Clock-Domain-Crossing-Issues/td-p/904824
2019-06-27 13:47:24 +03:00
65fea6c4c0
ad_ip_jesd204_tpl_dac: Fix up_axi instantiation
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This patch will fix the following warning:
[Synth 8-689] width (16) of port connection 'up_axi_awaddr'
does not match port width (12) of module 'up_axi'
2019-06-27 13:47:00 +03:00
acf6d618dd
util_clkdiv: fix for multiple instances
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Vivado propagates and auto derives the clocks, however if multiple
instances of this components are used the names of the propagated clock
change while the constraint file has fixed name which will match only
the clocks from the first instance letting the second instance of the
clock div without exception.
2019-06-27 10:33:51 +03:00
fd6a395347
axi_fmcadc5_sync: rename generated spi clock
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Rename the clock so it won't conflict with the main spi clock name.
2019-06-26 16:10:07 +03:00
1c99fde06b
axi_ad9361: Fix Intel interface - technology encoding update
2019-06-25 15:40:51 +03:00
01081c93e8
axi_ad9361: Fix the interface for Intel devices
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Use missing MIMO_ENABLE parameter, which will insert
and additional de-skew logic to prevent timing issues coming from
the clock skew differences of two or multiple AD9361.
2019-06-25 15:40:51 +03:00
Istvan Csomortani
Sergiu Arpadi
Laszlo Nagy
AndreiGrozav