Automate table generation for register maps.
Based on tfcollins' vger python scripts.
There are docs/adi_regmap_*.txt with more than one regmap per file,
so the logic changed to allow that.
Using title tool as the unique identifier now.
It has a global option to set the default state (hidden or visible)
for the collpasible tables.
Also remove CSVs.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Uses Vivado generated components.xml files.
If the file is not found/generated, there is a fallback method.
Also, define bibliography per project, not globally.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
The parameters directive allows to almost automatically generate the
parameters table.
It allows to add rich descriptions to the parameters, such as references,
while checking if they exist in the *_hw.tcl file a obtaining the types
and default values.
However, it cannot obtain parameters generated from a foreach loop yet,
making it incompatible with the axi_dmac_hw.tcl file for example.
This commit also joins the other extensions into a single adi_links
extension.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
* Added copyright and license header
* Updated files on which it runs on
* SystemVerilog not to be supported, since now there are some pkg files
that do not have the format of a Verilog file, thus making the
checker to fail all the time -- which is not good
* Now it can run on files which contain JESD in their paths, because
now all of them have the copyright on the same line (but the
copyright inside the JESD license can't be checked yet by the script)
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
docs/regmap/adi_regmap_adc.txt:
- add softspan to regmap
library/common/up_adc_channel.v
- update copyright year header
- add softspan to regmap
library/common/up_adc_common.v
- update minor version
Signed-off-by: John Erasmus Mari Geronimo <Johnerasmusmari.Geronimo@analog.com>