4fb6589b2d
pzsdr/ccfmc: add fan controls
2016-02-19 16:40:54 -05:00
377461e0d4
Merge branch 'hdl_2015_r2' into dev
2016-02-19 14:15:27 +02:00
0f37dd6424
fmcjesdadc1: Fixed project
...
- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
2016-02-19 14:09:57 +02:00
ce760eb691
fmcadc2- add adf4355 access
2016-02-18 16:17:33 -05:00
d94f157454
arradio: Changed ADC/DAC DMA address length to 24 bit
2016-02-16 15:27:51 +02:00
43e03ca6f7
arradio: Updated project
...
- made the reset bridges asynchronous
- connected the arradio gpio to the CPU interconnect
2016-02-16 14:50:23 +02:00
5518c47ca4
daq1_cpld: Set Input and tristate I/O termination mode to FLOAT
2016-02-15 19:27:59 +02:00
051ac307e6
daq1_cpld: Do not forward the first eight clock cycles of fmc_spi_sclk to sclk
2016-02-15 19:26:58 +02:00
9370246cfa
daq1: Fix bugs on CPLD design
...
Fix the CSN forwarding.
2016-02-12 16:59:09 +02:00
5ed2c0b599
daq1: Update CPLD constraints file
2016-02-12 16:54:36 +02:00
aa2ff0223a
daq1: Update CPLD design
...
+ SPI counter counts on negative edge of the SPI_CLK
+ Shift register for read, shifting MSB first
+ Fix write access logic
+ Update the internal register addresses
2016-02-12 14:45:18 +02:00
c32d7147d5
daq1 : There is a single CSN from master
2016-02-12 14:38:32 +02:00
9675df15c6
daq1_zc706: Update constraints file
2016-02-12 14:37:02 +02:00
e381d5170c
util_tdd_sync: Update the synchronization interface
...
Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-12 14:27:37 +02:00
61f9f72a75
fmcjesdadc1: Updated VC707 project for maximum throughput from DMA to DDR
...
- Increased the DMAs internal FIFO
2016-02-09 12:30:56 +02:00
c431adb793
fmcjesdadc1: Updated KC705 project for maximum throughput from DMA to DDR
...
- Increased the DMA internal FIFO
2016-02-09 12:00:27 +02:00
ad9ecbbbb6
daq2: Updated a10gx project to quartus 15.1.1
2016-02-05 17:43:05 +02:00
a74e2061e9
ad7616_sdz: BUSY is input for the FPGA
2016-02-03 14:12:00 +02:00
bb62f6d225
pzsdr1- updates
2016-02-02 12:34:09 -05:00
41b6ebeeaf
pzsdr1- updates
2016-02-02 12:33:55 -05:00
b147e9c94a
pzsdr1- updates
2016-02-02 12:33:01 -05:00
59783f6cff
ad7616_sdz: Add support for Zedboard
2016-01-29 15:28:06 +02:00
122667259f
ad7616_sdz: Update Make file
2016-01-28 14:48:44 +02:00
118577f64f
ad7616_sdz: Add support for parallel interface
2016-01-28 12:38:22 +02:00
170295161f
pzsdr1- xdc
2016-01-26 11:19:00 -05:00
cd43ebd8bc
axi_ad7616: The OP_MODE parameter is no longer required
2016-01-26 11:05:33 +02:00
bcac3eef4d
pzsdr1- initial commit
2016-01-25 16:07:33 -05:00
44a382fc69
pzsdr1-added
2016-01-25 15:33:34 -05:00
2a17ce275c
axi_ad7616: Control inputs are controlled through GPIO
...
The following control inputs are controlled through GPIO: reset_n, seq_en, hw_rngsel, chsel, crcen, burst and os.
2016-01-25 17:50:50 +02:00
e22d5d5c18
daq2: Fix clock constraints for KC705 and VC707
2016-01-22 19:09:57 +02:00
59fbd99fdb
fmcjesdadc1: Added clock constraint for the ADC path
2016-01-22 15:46:20 +02:00
dca39c26f9
ad6676evb: Added clock constraint for the ADC path
2016-01-22 15:45:16 +02:00
9cd0378003
fmcadc2: Added clock constraint for the ADC path
2016-01-22 15:44:04 +02:00
aa77af6bdf
daq1_cpld: Add ISE project file
...
This file, along with the project source files, is sufficient to open and implement in ISE Project Navigator.
2016-01-21 18:05:59 +02:00
14f7027793
ad7616_sdz: Move the context switching to system_project.tcl
2016-01-19 11:34:28 +02:00
8c69c9d2ce
daq1_zc706 : Update the project
...
+ Add AD9684 to the block design
+ Update the IO definitions
+ Update the CPLD design
+ Add 3wire SPI logic
2016-01-19 11:20:35 +02:00
ab99c4456a
ad9434_fmc: Delete unnecessary set_property call
...
HPx interface is activated by the ad_mem_hpx_interconnect process
2016-01-14 15:41:23 +02:00
c094ab8b52
cn0363: Add support for the MicroZed
...
Add support for connecting the CN0363 to the MicroZed. This works in
combination with the MicroZed Arduino carrier board. The CN0363 needs to be
connected to the PLPMOD header.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:32:26 +01:00
514eb68876
cn0363: Factor out common parts
...
Factor out the common parts of the cn0363 design so we can use it to add
support for other carriers.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:32:26 +01:00
d2b26720e6
common: microzed: Add clock, reset and interrupt support
...
In order for the base project to be usable by other projects it needs to
create the clock, reset and interrupt signals that are expected to exist.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:32:26 +01:00
51d20b1a61
adi_project.tcl: Add MicroZed support
...
Handle the projects for the MicroZed and set up the FPGA part accordingly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:32:26 +01:00
426490c394
common: Rename uzed to microzed
...
Everybody calls the MicroZed microzed in their projects. Don't deviate from
that to avoid potential confusion.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:18:57 +01:00
c397787001
uzed: updates
2016-01-11 15:36:01 -05:00
a610ebb413
uzed: zed-copy
2016-01-11 13:53:22 -05:00
02cc926275
daq1: Add CPLD logic and IO constraints
2016-01-04 18:10:46 +02:00
7013b319b0
motcon2_fmc: Fixed reset connection for cpack cores
2015-12-22 12:03:34 +02:00
17e7d1b86f
ad7616: Add Makefiles
2015-12-21 17:09:42 +02:00
2bb19be3d3
pzsdr/ccfmc: sfp io control
2015-12-17 16:18:06 -05:00
f3fe16a102
pzsdr/ccfmc: camera/sfp pin changes
2015-12-17 16:17:24 -05:00
ea045a3f9a
fmcadc4: change qpll to receive
2015-12-17 12:34:47 -05:00
40ab2f5e6a
ccfmc: tdd/gpio bit moved to the top
2015-12-17 11:37:57 -05:00
34b832e22a
fmcomms6: Fixed reset connection for cpack core
2015-12-16 10:36:33 +02:00
35f6bd16e9
fmcomms5: Fixed reset connection for cpack core
2015-12-16 10:34:36 +02:00
83fd4a53a7
daq3/kcu105: updates
2015-12-14 09:29:48 -05:00
07316a905e
daq3/a10gx: sysref is lvds
2015-12-14 09:29:10 -05:00
ee4d5af12e
ad7616_sdz: Update the project
...
+ Fix system_top.v
+ Finish up the common block design
+ Fix system_project.tcl
2015-12-14 16:02:38 +02:00
f4e3523390
ad7616_sdz: Update IO constraints
2015-12-14 15:34:56 +02:00
6a9d1c431a
daq3/a10gx: updated to a10gx/quartus
2015-12-11 12:49:25 -05:00
da2e1bdc9a
daq2/a10gx: 32bits generic gpio
2015-12-11 11:50:26 -05:00
650d426301
a10gx/base: set gpio to 32
2015-12-11 10:14:37 -05:00
dc84a9ad82
daq3/a10gx: updates
2015-12-10 16:06:14 -05:00
f1b6577447
a10gx/base: separate gpio in/out
2015-12-10 16:04:54 -05:00
d944198212
daq3/a10gx: board updates
2015-12-10 09:45:20 -05:00
1a38ea205d
daq3/a10gx: copy
2015-12-10 09:42:56 -05:00
614babc18e
daq3/kcu105: copy
2015-12-10 09:41:47 -05:00
b0fef1122e
daq3/a10gx: copy
2015-12-10 09:41:37 -05:00
be075379df
hdlmake: updates
2015-12-07 13:11:24 -05:00
0938041d97
ad7768evb: added
2015-12-07 13:07:03 -05:00
6e549171f0
fmcomms5: Connected the clk input of the ad9361 to l_clk
2015-12-02 14:43:44 +02:00
2309c4d83c
Makefiles: Removed " from path
2015-11-27 14:02:46 +02:00
159f6c1216
Makefiles: Updated Makefiles
...
- for altera projects, taken into consideration of the new location for common qsys files
- for fmcomms5, added wfifo dependency
- for daq3, added mfifo dependency
2015-11-27 12:39:42 +02:00
36febf8591
Merge branch 'master' into dev
...
Conflicts:
library/axi_ad9361/axi_ad9361_ip.tcl
library/axi_dmac/Makefile
library/axi_dmac/axi_dmac_constr.ttcl
library/axi_dmac/axi_dmac_ip.tcl
library/common/ad_tdd_control.v
projects/daq2/common/daq2_bd.tcl
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
projects/fmcomms2/zc706pr/system_project.tcl
projects/fmcomms2/zc706pr/system_top.v
projects/usdrx1/common/usdrx1_bd.tcl
This merge was made, to recover any forgotten fixes from master,
before creating the new release branch. All conflicts were reviewed
and resolved.
2015-11-26 13:38:11 +02:00
ea57b3c03c
daq2: A10GX, add project specific IP search paths
2015-11-25 10:58:36 +02:00
e8a595b81e
fmcjesdadc1: Updated a5soc design
2015-11-24 15:39:52 +02:00
fd3910a915
fmcjesdadc1: Updated a5gt design
2015-11-24 15:39:21 +02:00
9281eb2c33
fmcjesdadc1: Updated common altera design
2015-11-24 15:38:58 +02:00
a81625e1fa
daq2: Updated a10gx project
2015-11-24 13:28:53 +02:00
605a0768e0
arradio: Updated c5soc project
2015-11-24 13:27:44 +02:00
a0e67aad56
c5soc: Updated common design
2015-11-24 13:22:01 +02:00
c051a578e5
fmcomms2: Delete unnecessary clock definition
...
The two clocks, rx_clk and ad9361_clk, are the same.
2015-11-20 19:35:37 +02:00
c15c82d9d1
ccpci- remove ps7 ddr hp0 access
2015-11-19 16:42:02 -05:00
4603bd222b
ccpci- set pcie io after ip
2015-11-19 16:42:01 -05:00
95af462409
ccpci- loc by pin-name is ignored
2015-11-19 16:42:00 -05:00
0f8d427aef
ccpci- remove ila
2015-11-19 16:41:58 -05:00
9cfbf0ea61
ccpci- add axi spi/gpio
2015-11-19 16:41:57 -05:00
a1601a03d6
pzsdr: added ad9361 clock out
2015-11-16 15:55:56 -05:00
8aefe569b8
pzsdr: output ad9361 clock out to fan io
2015-11-16 15:54:30 -05:00
597e9eae84
pzsdr: added ad9361 clock out
2015-11-16 15:53:29 -05:00
a6f44949d6
daq3: updates
2015-11-13 13:17:11 -05:00
c88cbf78af
fmcomms5: Added wfifo at the between AD9361 and cpack core
2015-11-13 15:50:32 +02:00
bec4c8da84
pzsdr: Update Make files
2015-11-11 11:16:05 +02:00
2345d29663
fmcomms2: Update make files
2015-11-11 11:15:45 +02:00
a936ad607f
fmcomms2/zc706: Delete unused files from file list
2015-11-11 11:14:58 +02:00
c7e86528d6
fmcomms2/zc706: Cosmetic changes on constraints file
2015-11-11 11:14:16 +02:00
6197a82c80
fmcomms2/common: Add the util_tdd_sync module
2015-11-11 11:07:15 +02:00
5cc97c78d3
Makefiles: Update makefiles to include the nerw axi_gpreg / util_mfifo libraries
2015-11-10 09:32:50 +02:00
ef9bdf6ec9
adi_project: Regenerate the layout of the IP Integrator subsystem design.
2015-11-09 11:01:10 +02:00
214adbfd85
ad7616_sdz_zc706: Add board related IO's to system top.
2015-11-09 10:51:46 +02:00
1d6254fdec
pzsdr/ccbrk: loopback board support
2015-11-06 11:34:21 -05:00
afc4274ee3
common scripts: Changed the resulting hdf file to system_top_bad_timing, if design doesn't meet timing.
2015-11-06 16:01:19 +02:00
0c7c0f2cd8
common scripts: Change the name of the generated HDF if the design doesn't meet timing
2015-11-05 18:41:51 +02:00
11718291cf
pzsdr/ccfmc- add single loopback core
2015-11-05 11:28:38 -05:00
9e27a60478
pzsdr/ccfmc- single loopback core
2015-11-05 11:28:33 -05:00
e36f27b061
daq2: Update A10GX project, with the latest changes.
...
Works with up to 64k samples
2015-11-04 14:54:09 +02:00
83399ef6ee
a10gx: Updated common project to work with Linux (enabled MMU)
2015-11-04 13:35:52 +02:00
27266c59ee
ad7616_sdz: Add project source files
2015-11-03 15:03:35 +02:00
a0039ed4fe
ccfmc: Launch HDMI data on falling edge
...
The ADV7511 captures data on the rising edge, so make sure to launch data
on the falling edge. This fixes some issues with image stability.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 10:59:13 +01:00
6dddac5d94
ccfmc- missing board io
2015-11-02 15:45:14 -05:00
cafc80c829
fmcadc5: add programmable io delay
2015-11-02 12:10:18 -05:00
8b95520767
pzsdr/ccfmc- add loopback gpio/gt cores
2015-10-30 18:48:26 -04:00
92b7570864
pzsdr/ccfmc- add ad9517 signals
2015-10-30 10:50:53 -04:00
b3cb84cf91
fmcadc5- added ila
2015-10-29 16:48:21 -04:00
24d76c610a
fmcadc5- fix core connections
2015-10-29 16:47:56 -04:00
ac4091e19e
fmcadc4- add monitor fifo
2015-10-27 14:52:02 -04:00
b5d3d0bd13
usb_fx3: Added axi_usb_fx3 core and DMA to the project
2015-10-27 09:41:18 +02:00
748a2bc87a
fmcadc4- add ila for zc706 only
2015-10-23 14:32:35 -04:00
b2d0f5c56e
fmcadc4- use the same source/name for clocks
2015-10-23 14:32:35 -04:00
9d2b8809df
Makefiles: Updated Makefiles
2015-10-23 10:44:27 +03:00
cb2bda48c0
fmcadc5- gt/ip updates
2015-10-19 09:31:32 -04:00
ed918ec119
imageon - keeping scripts happy
2015-10-16 15:04:02 -04:00
e14e9294c5
project-names -- variables causes scripts to fail- too much parsing
2015-10-16 14:13:56 -04:00
36dd6427fe
pzsdr: Add untracked Makefiles
2015-10-16 13:58:36 +03:00
bbdc693954
pzsdr/all: Update Makefile
2015-10-16 11:57:51 +03:00
08777ca566
fmcadc5- latest board changes
2015-10-15 10:46:07 -04:00
030485de28
fmcadc5- regulators need a switching ref clock?
2015-10-15 10:46:07 -04:00
f966f79e5f
fmcadc5- regulators need a switching ref clock?
2015-10-15 10:46:07 -04:00
199227b78c
fix fmcjesdadc1_bd ILA warning
2015-10-13 10:19:08 -04:00
21737ad7b8
fmcomms2/zc706pr: Update the fifo interface of the PR module
2015-10-13 11:37:44 +03:00
c9a5057b93
library/prcfg : Split data bus to channels
...
Because of the new pack/upack modules on the data path, it makes more sense to split the data interface of the PR modules into separate channels.
The top module will supports max 4 channels.
2015-10-13 11:36:45 +03:00
9bb70e2b69
motcon2_fmc: Updated ZED project
2015-10-09 15:33:31 +03:00
83fb5c742a
motcon2_fmc: Updated project to Vivado 2015.2.1
...
- added cpack cores
- removed controller DMA paths
2015-10-09 13:56:41 +03:00
88e8bef92f
usdrx1: Update ZC706 project
2015-10-09 13:33:45 +03:00
02c0a5f5df
usdrx1: Update project to Vivado 2015.2.1
2015-10-09 13:33:07 +03:00
c83239b014
fmcomms2/zc706pr: Update PR design
...
+ Add system_top.v to design
+ Add pr specific constraints
2015-10-09 13:23:42 +03:00
09be227db9
fmcomms2/zc706pr: Update PR design
...
+ Add system_top.v to design
+ Add pr specific constraints
2015-10-09 13:19:09 +03:00
e4517c0d6a
daq2/common: Connect reset to dac fifo
2015-10-08 16:51:08 +03:00
df88b33946
usb_fx3: Initial commit
...
Only the UART connections are available.
The FMC should not be populated at this time
2015-10-02 09:30:31 +03:00
b93af3c21e
daq3- bd updates
2015-09-30 10:11:49 -04:00
81a1c21553
util_pmod_adc: Reset line changed to active low reset.
2015-09-30 12:33:46 +03:00
5f12c8c7d4
cftl_cip/common: Fix parameter names for dmac
2015-09-30 12:32:48 +03:00
3dc881dbb3
pmods/xfest14: Delete directory
...
This project will not be supported from the next release
2015-09-30 12:25:31 +03:00
e6af671bea
cn0363/zed: Fix DMAC parameter names
2015-09-30 11:31:53 +03:00
4aa4ffc25f
imageon/common: Update cores to Vivado 2015.2
2015-09-29 18:51:46 +03:00
e60d2f86b3
imageon/common: Fix parameter name for spdif_rx
2015-09-29 18:50:41 +03:00
b4252a8512
imageon_loopback: Delete directory
...
This project will not be supported from the next releases.
2015-09-29 14:53:44 +03:00
9832cea071
ad9739a_fmc: Common, reduced DMA fifo size
2015-09-28 12:19:23 +03:00
5b48340b08
fmcomms6: Updated ZC706 project
2015-09-28 11:32:20 +03:00
3b3c645827
fmcomms6: Updated project to Vivado 2015.2.1. Added cpack
2015-09-28 11:31:08 +03:00
046c89dacd
fmcomms2/pr: Delete the fmcomms2_pr directory
...
The fmcomms2/pr project is moved to fmcomms2/zc706pr
2015-09-25 19:11:43 +03:00
f77f928444
fmcomms2/zed: Fix the system_top
...
Fix the enable/txnrx control line.
2015-09-25 19:11:41 +03:00
aeb1d7aa3e
fmcomms2/zed: Cosmetic changes
2015-09-25 19:11:39 +03:00
f8b3096bd0
fmcomms2/vc707: Fix the system_top
...
Fix the enable/txnrx control lines.
2015-09-25 19:11:37 +03:00
2c75cfd04e
fmcomms2/vc707: Cosmetic changes
2015-09-25 19:11:35 +03:00
ffa0bcd19f
fmcomms2/mitx045: Fix the system_top
...
Fix the enable/txnrx control lines.
2015-09-25 19:11:32 +03:00
28d20e84c5
fmcomms2/zc702: Fix the system_top
...
Fix the enable/txnrx control lines.
2015-09-25 19:11:30 +03:00
ea74413125
fmcomms2/kc705: Fix the system_top.
...
Fix the enable/txnrx control lines.
2015-09-25 19:11:28 +03:00
f80622b972
fmcomms2/ac701: Fix the system_top
...
Fix the enable/txnrx control line.
2015-09-25 19:11:26 +03:00
07e2d281c0
Make: Update Make files
2015-09-25 19:11:21 +03:00
1604e88242
fmcadc4: Update project to the new JESD interface framework
2015-09-25 19:11:19 +03:00
f4b432da08
fmcadc4: Update to 2015.2
2015-09-25 19:11:17 +03:00
4f99bdd93f
fmcadc5: Update project
...
+ Update the JESD IP core for Vivado 2015.2
+ Update the framework for JESD interface
2015-09-25 19:11:14 +03:00
f5b5bbfbca
fmcomms7: Update to the new JESD framework
...
Update project to the new framework for JESD interface and add a DAC FIFO to the transmit path.
2015-09-25 19:11:12 +03:00
fbd51c2734
fmcomms7: Update to 2015.2
...
Update IP core version of jesd204.
2015-09-25 19:11:10 +03:00
d198caa621
fmcomms2: Updated ZC702 design
2015-09-25 18:15:40 +03:00
4b115fbe69
ad9467_fmc: Delete ILA from the design
2015-09-25 17:41:46 +03:00
7853843036
fmcomms5: Update ZC706 project
2015-09-25 17:32:29 +03:00
108ffebae4
fmcomms5: Updated project to 2015.2.1
...
- added cpack / upack
2015-09-25 17:31:08 +03:00
848b51699c
fmcadc2: Updated VC707 project
2015-09-25 17:28:15 +03:00
e764f54426
fmcadc2: Updated ZC706 project
2015-09-25 17:26:54 +03:00
6fbd8dd9a5
fmcadc2: Update projecct to 2015.2.1
...
- updated to the new jesd framework
2015-09-25 17:25:32 +03:00
ab4b73fd32
ad6676evb: Updated VC707 project
2015-09-25 16:07:22 +03:00
33390c85f8
ad6676evb: Update ZC706 project
2015-09-25 14:46:02 +03:00
a49230ec07
ad6676evb: Updated project to 2015.2.1
...
- updated to the new jesd framework
- added cpack core
2015-09-25 14:44:46 +03:00
7f9c526683
fmcjesdadc1: VC707 update project
2015-09-24 19:50:14 +03:00
78fe05120b
fmcjesdadc1: Updated KC705 project
2015-09-24 19:14:48 +03:00
70c7c2aeb8
fmcjesdadc1: Updated ZC706 project
2015-09-24 19:14:05 +03:00
2ed161628d
fmcjesdadc1: Updated project to 2015.2.1
...
- updated to the new jesd framework
- added cpack core
2015-09-24 19:12:40 +03:00
58ab70bc0e
fmcomms1: Update AC701 project
...
Renamed mdio pin, as it's exported by the system wrapper
Renamed DMA parameter
2015-09-24 19:07:19 +03:00
f9801e8c85
pzsdr/cc*- rf card on fmc only
2015-09-23 09:16:41 -04:00
9832ea95a8
pzsdr/ccpci- initial version
2015-09-22 16:30:27 -04:00
14bccb6062
pzsdr/ccfmc- rf card/tdd only on fmc
2015-09-22 15:54:53 -04:00
fa5d879fdb
pzsdr/ccpci -- updates
2015-09-21 14:54:31 -04:00
fce96099ab
unused eth1 clocks
2015-09-21 14:54:31 -04:00
0702f2c231
ccpci- added
2015-09-21 09:31:18 -04:00
3a72d26f5b
pzsdr- pci carrier
2015-09-18 21:18:16 -04:00
9f8433159f
pzsdr- name changes
2015-09-18 16:24:27 -04:00
0d232a270a
pzsdr- breakout + fmc updates
2015-09-18 15:34:56 -04:00
3bd2bc4071
pzsdr- breakout + fmc updates
2015-09-18 15:34:36 -04:00
25f3f05c22
pzsdr- breakout + fmc updates
2015-09-18 15:33:50 -04:00
93b928033b
ccbrk- added
2015-09-18 13:24:26 -04:00
caec400378
pzsdr- make module default
2015-09-18 13:22:01 -04:00
236854c26f
pzsdr-cc-fmc updates
2015-09-18 12:46:42 -04:00
f970bf1786
pzsdr fmc carrier
2015-09-18 11:50:08 -04:00
b3a4f11e97
rfsom to pzsdr
2015-09-18 11:48:30 -04:00
0386bedff9
fmc carrier is -- ccfmc
2015-09-18 11:45:56 -04:00
92533bc24d
fmc carrier is -- ccfmc
2015-09-18 11:45:15 -04:00
48af5f29de
rfsom renamed to pzsdr
2015-09-18 11:19:50 -04:00
3ef94d559c
rfsom renamed to pzsdr
2015-09-18 11:18:59 -04:00
52d3f189a0
rfsom renamed to pzsdr
2015-09-18 11:18:01 -04:00
e2886eaa44
pzpcie- updates
2015-09-18 11:10:48 -04:00
379f788c8c
pzpcie- added
2015-09-18 11:10:48 -04:00
9e68357af5
usdrx1: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:19 +02:00
275830d2b1
motcon2_fmc: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:17 +02:00
8d179235f8
imageon: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:14 +02:00
9210e1d58a
fmcomms7: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:11 +02:00
39b032b868
fmcomms5: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:09 +02:00
cd8b467b1e
fmcomms2: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:07 +02:00
7e2255f4d9
fmcjesdadc1: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:05 +02:00
dd79dfdc12
fmcadc5: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:03 +02:00
7f5a22a75f
fmcadc4: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:01 +02:00
60490c4e2b
fmcadc2: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:59 +02:00
6c7316fbd0
daq3: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:56 +02:00
7184827d68
daq2: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:54 +02:00
f1fb599eb1
cn0363: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:51 +02:00
6d87f537da
cftl_cip: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:49 +02:00
1c603b830e
ad9467_fmc: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:47 +02:00
960c711f3b
ad9434_fmc: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:44 +02:00
7be1f62b8b
ad9265_fmc: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:25 +02:00
0f553a08e8
ad6676evb: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:21 +02:00
0021c7869d
kc705: Deactivated narrow burst support, as it's not needed
2015-09-16 19:02:17 +03:00
70cea5b14e
fmcomms1: Removed ILA
2015-09-16 18:51:40 +03:00
63aaa58861
ad9265_fmc: Updated project, removed ILA related clocks
2015-09-11 11:27:58 +03:00
a679251d7d
Makefiles: Update Make
2015-09-09 17:13:19 +03:00
f3eca48533
pzsdr_rfsom: Update project with the new TDD sync interface
2015-09-09 12:37:52 +03:00
510f1cfdd9
fmcomms2_zc706: Update project with the new TDD sync interface
2015-09-09 12:35:22 +03:00
f428d8bde9
adv7511: KC705, updated design so that the axi_hdmi_dma core has memory connection datawidth of 512
2015-09-08 16:43:40 +03:00
d81d8238a9
kc705: Updated mig project file
2015-09-08 16:42:23 +03:00
2757cd8baf
adv7511: AC701 fixed system top
2015-09-07 16:48:10 +03:00
214f5b18c1
no-trace option
2015-09-03 16:16:31 -04:00
00a55ded00
ibert to jesd-gt change
2015-09-03 16:16:30 -04:00
77ee3c4cbc
ibert to jesd-gt change
2015-09-03 16:16:28 -04:00
dbf7c154b2
no-trace option
2015-09-03 16:16:27 -04:00
e2aca435e5
ibert-to-jesd-gt change
2015-09-03 16:16:25 -04:00
f1d416a98b
daq2/a10gx- ethernet fix
2015-09-02 14:31:15 -04:00
1fff1076b1
daq2/a10gx- ethernet fix
2015-09-02 14:31:15 -04:00
01c0fdc809
daq2/a10gx- ethernet fix
2015-09-02 14:31:15 -04:00
1ecd615f92
common/mitx045 : Fix the vdma interface of axi_hdmi_core
2015-09-02 16:33:30 +03:00
9fb336e464
usdrx1: Add DDR FIFO
...
The converters on the usdrx1 generate 2.5GB/s. This more than we can
transport over the HP interconnects to the system memory.
Add a dedicated DDR FIFO to design which can be used to buffer the data
before it is transferred to the main memory.
Also increase the interconnect clock rate from 100MHz to 200MHz and the DMA
FIFO size from 4 to 8, so we can transfer the captured data faster to the
main memory.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
bbada6ed8f
usdrx1: Add overflow flag to ILA
...
It's useful to know if and when a overflow happens.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
c67aecc1eb
usdrx1: Disable SYNC_TRANSFER_START for the DMA
...
There is no sync signal in this design, so the flag needs to be set to 0.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
c00a6af4db
usdrx1: Add DDR FIFO
...
The converters on the usdrx1 generate 2.5GB/s. This more than we can
transport over the HP interconnects to the system memory.
Add a dedicated DDR FIFO to design which can be used to buffer the data
before it is transferred to the main memory.
Also increase the interconnect clock rate from 100MHz to 200MHz and the DMA
FIFO size from 4 to 8, so we can transfer the captured data faster to the
main memory.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:21:45 +02:00
b73430d7ee
usdrx1: Add overflow flag to ILA
...
It's useful to know if and when a overflow happens.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:21:45 +02:00
b7de542e26
usdrx1: Disable SYNC_TRANSFER_START for the DMA
...
There is no sync signal in this design, so the flag needs to be set to 0.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:21:45 +02:00
9b37d6bfe7
pzslb- updates - wip
2015-08-31 15:41:29 -04:00
49430dc2b0
pzslb- copy
2015-08-31 15:41:27 -04:00
879a75a690
pzslb- copy
2015-08-31 15:41:26 -04:00
fdc3dbb805
pzslb- copy
2015-08-31 15:41:25 -04:00
fc79af6edc
pzslb- common
2015-08-31 15:41:24 -04:00
f005de9ee2
pzslb- added
2015-08-31 15:41:23 -04:00
a67ae238f8
rfsom-ps7- ddr settings
2015-08-31 15:39:45 -04:00
Rejeesh Kutty
Adrian Costina
Istvan Csomortani
István Csomortáni
Lars-Peter Clausen
Nicholas Pillitteri