Commit Graph

10 Commits (073718315a39b357dc0225a5e4c77149be4295e6)

Author SHA1 Message Date
Rejeesh Kutty edd5e9570f file renamed; sed output; fingers crossed 2017-02-22 15:56:37 -05:00
Istvan Csomortani f47863bbcf usdrx1: Integrate ad_syref_gen into the project 2016-12-19 14:36:01 +00:00
AndreiGrozav d962614000 usdrx1/zc706: Disabele axi_spi constraint file
The interface ports of the AXI SPI IP are not connected
  directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:23:51 +02:00
Adrian Costina 284fbac571 usdrx1: Xcvr updates, so that the channel parameters are correctly configured from boot time 2016-11-28 14:16:07 +02:00
Lars-Peter Clausen 9fb336e464 usdrx1: Add DDR FIFO
The converters on the usdrx1 generate 2.5GB/s. This more than we can
transport over the HP interconnects to the system memory.

Add a dedicated DDR FIFO to design which can be used to buffer the data
before it is transferred to the main memory.

Also increase the interconnect clock rate from 100MHz to 200MHz and the DMA
FIFO size from 4 to 8, so we can transfer the captured data faster to the
main memory.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Adrian Costina 037484e1d0 usdrx1: Updated project to the latest framework 2015-03-25 17:39:51 +02:00
Adrian Costina d33fb07587 usdrx1: Modified the GPIO assignments so that board specific GPIOs start from GPIO 32.
GPIOs for which the directions is known, have been specifically assigned.

The SPI clock has been changed to a lower frequency.
2014-09-16 15:56:19 -04:00
Rejeesh Kutty 96541f0a7f usdrx1: zc706 updated for usdrx1 2014-04-10 11:05:13 -04:00
Rejeesh Kutty ac1c145a61 usdrx1: initial checkin 2014-04-10 11:05:10 -04:00