The DDR memory reference clock on the A10SoC development board is
differential. Currently the EMIF core it is configured for single-ended
configuration, which causes it to generate incorrect IOSTANDARD
constraints. Those incorrect constraints get overwritten again in
system_assign.tcl, so things are working, but this generates a warning when
building the design
Configure the EMIF core correctly and remove the manual constraint overwrite since
they are no longer necessary.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
While things seem to work fine with only specifying the the IO standard for
the positive side of differential signals Quartus will issue a warning
about incomplete constraints if the IO standard is not specified for the
the neagtive side as well. To avoid these warnings add the missing
constraints.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Fix a copy and paste error and specify the IO_STANDARD for all gpio_bd_i
rather than twice for half of them.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Adrian Costina
Lars-Peter Clausen
Rejeesh Kutty
AndreiGrozav