On large projects with multiple channels the databus on the FIFO/AXI
stream interface can get wider that 1024 bits.
This commit allows a wider range for all the interfaces,
in case for the memory mapped interfaces where the range is 32-1024 the
user selects a bus width out of range that will be handled by the IPI.
This adds a Readme.md to each project directory with pointers to project
documentation in the wiki, and the drivers (if they exist). This will
help with some autogenerated doc in the wiki, that is generated with the
innovatily named "wiki_summary.sh" shell script that parses through
these Readme.md files, and generates a summary table.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Iacob Liviu Mihai <liviu.iacob@analog.com>
Occasionally with zed, the implementation failed at the placement stage where
the tool could not fit the logic cells inside a single clock region,
constraint required by the usage of regional clock buffers.
This commit allows the usage of the global clock buffers which help the tool
in such cases and allow a larger application logic to be implemented in fabric.
Fix CONVERTER_RESOLUTION parameter setting for ad9250. Also deleted the
setting of BITS_PER_SAMPLE and DMA_BITS_PER_SAMPLE for ad9250 since they
are set by default to the desired values.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
For CMOS case, lane rates are so low that reference clock of the source
synchronous interface can be routed on non-clock routes. The delays on
the clock line are adjusted by the digital interface tuning controlled
through software.
Lock down clock buffers on Rx and Tx interfaces, this avoids suboptimal
placement which causes large skew between clocks at the serdes pins.
1. Reduce max allowed skew between source synchronous clocks that can
occur due PCB differences. 250ps represents a difference more than an
inch.
2. In order to reduce skew between source synchronous clock and the
divided clock instruct the tool to use a common clock root for them.
The 4 parameters are added to facilitate transmiting project
related information to the software. They act as read-only
memory which is written in Vivado when the project builds.
Set 31 to SDI FIFO's almost full threshold
In case of multiple SDI (MISO) lanes, the samples arrives in a parallel
fashion. For example in case of 4 MISO line, at the first latching clock
edge 4 bits of a sample will be saved, one bit into each shift register.
The data reorder module reconstruct the incoming samples from the AXI
stream of the offload module.
Laszlo Nagy
Robin Getz
LIacob106
Nicola Corna
Dan Hotoleanu
stefan.raus
Stanca Pop
hotoleanudan
Filip Gherman
David Winter
sergiu arpadi
Istvan Csomortani
Mihaita Nagy