1407bebb11
kcu105: Changed the interrupt net names to be similar to other microblaze based projects
2015-03-18 13:47:37 +02:00
f3188b917b
common-base-designs: add intr net names
2015-03-12 15:56:31 -04:00
3654be4766
common-base-designs: add intr net names
2015-03-12 15:56:25 -04:00
c1dc93e2c7
common-base-designs: add intr net names
2015-03-12 15:56:15 -04:00
91c87b8438
common-base-designs: add intr net names
2015-03-12 15:56:06 -04:00
63a390af49
common-base-designs: add intr net names
2015-03-12 15:55:59 -04:00
f3c41cd9aa
common-base-designs: add intr net names
2015-03-12 15:55:50 -04:00
8456523084
common-base-designs: add intr net names
2015-03-12 15:55:41 -04:00
21f884e346
kc705/vc707: intr sensitivity fix
2015-03-11 15:03:43 -04:00
ad105b9c54
kc705/vc707: intr sensitivity fix
2015-03-11 15:03:35 -04:00
890bb1da75
daq2: Add support for VC707
2015-01-29 18:33:27 +02:00
623e732ee6
kc705: Updated base project with linear flash. Updated all depending projects
2015-01-13 10:07:51 +02:00
a6cf615ee0
zc706_constr: Move the sys_rst related constraint definition to zc706_system_mig_constr.xdc
2014-12-19 13:00:35 +02:00
daba3fb72e
plddr3: sys-rst from board pushbutton
2014-12-19 12:59:42 +02:00
758ac6bb8e
plddr3: sys-rst from board pushbutton
2014-12-19 12:59:35 +02:00
1a9eb8196a
VC707: Fixed linear flash timings
2014-12-18 17:49:00 +02:00
9e8fd8ed9e
base_design: External IIC reset is connected to Vcc
...
External IIC reset is connected to Vcc in case of AC701, KC705 and VC707
2014-12-11 11:14:54 +02:00
842ba19aaa
fmcomms2/ml605: compilation fixes
2014-12-09 14:31:12 -05:00
2e4640d5c5
ad9467_kc705: Fix memory segment offset for SEG_axi_ddr_cntrl
2014-12-09 16:17:46 +02:00
84174460bb
projects/common/kcu105/kcu105_system_bd: Restore axi_ethernet SupportLevel 0
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Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-05 14:50:45 +01:00
bb6cc40902
projects/common: KCU105 VC707 update and sync axi_ethernet:6.1 features
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Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-05 14:50:45 +01:00
8e4d0a1b60
projects/common: KCU105 VC707 KC705 sync microblaze core defaults
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Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-05 14:50:45 +01:00
11f41d1dff
zynq_plddr3: Fix PLDDR3's Reset Generator
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Reset generator's external reset signal was active low, but the GT reset is active high, and both the DDR controller and FIFO2S were in reset.
Therefore the external reset active state is changed to active high. This setup in general is made by the tool automatically, in order to do it correctly, need to
set this two property of the reset generator.
2014-12-04 15:42:28 +02:00
419d38b9f6
kc705_base: Define sys_addr_mem_seg for dmafifo
2014-11-26 15:38:41 +02:00
c0f4d7e2b5
mitx045_common: Definition file patch
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In 2014.2 tool version, the way how a definition file needs to be applied is different
The command "apply_bd_automation" should be used, instead setting property PCW_IMPORT_BOARD_PRESET
In non-project mode (PR design flow), after creating the static design the type of the board is set.
NOTE: the definition file for mitx must be installed accordingly in order to get this work
See link: http://zedboard.org/support/documentation/2056
2014-11-21 19:14:37 +02:00
cdd1408d3c
dmafifo: parameterized address width
2014-11-20 09:28:02 -05:00
e3378cd6cb
mitx045_board_definition: revert old board definition file
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Revert commit 4f6aa159b8
2014-11-18 10:05:55 +02:00
5baa015246
kc705_base: Delete timing constraints
2014-11-13 16:30:37 +02:00
074662a622
dmafifo: common interface with fifo2s
2014-11-12 15:24:31 -05:00
c6af2696b3
plddr3: internal buswidth/clock conversion
2014-11-12 14:43:48 -05:00
05ed98f884
common: Updated common constratins for ac701, kc705, vc707, zc702
2014-11-11 12:35:44 +02:00
2d9a529ab8
kcu105: ddr - 800M
2014-11-06 16:50:37 -05:00
4634a4f868
vc707: Added linear flash to the base design
2014-11-05 17:18:40 +02:00
4f815b99a1
kc705_base: Fix sys_concat_intc input connections
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All the unused input pins need to be connected to ground.
2014-11-03 13:02:08 +02:00
f7588131da
ac701_base: Interrupt update
2014-11-03 13:02:04 +02:00
b92636c6eb
kc705_base: Interrupt update
2014-11-03 13:02:03 +02:00
16cdae3001
mitx045_base: Delete unnecessary timing constraints.
2014-10-31 11:50:49 +02:00
67bec719f7
mitx045_base: Interrupt update
2014-10-31 11:45:33 +02:00
56859ad4c9
sys_dmafifo: use internal memory
2014-10-30 15:26:28 -04:00
7ae003cf82
zed_base: Interrupt update
2014-10-30 19:00:05 +02:00
ba53e156e3
ZC702_base: Interrupt update
2014-10-30 18:39:49 +02:00
f595b86576
kcu105: lutram constraints for ies
2014-10-30 11:20:27 -04:00
4c0e4d280f
dmafifo: internal version- light duty
2014-10-30 11:12:13 -04:00
360e7104b6
dmafifo: axi version- heavy duty
2014-10-30 11:12:12 -04:00
2e01ad2eec
ad9625_fmc/zc706: ps7 interrupt updates
2014-10-29 12:13:44 -04:00
f83622a2e6
daq2/kcu105: interrupt updates
2014-10-28 15:51:42 -04:00
4788d09620
vc707: interrupt updates
2014-10-28 15:42:55 -04:00
a870603db5
common_bd: Update the common block designs to the new IRQ path
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Avoid the use of xil_concat module by using the ad_interrupts.
2014-10-27 19:44:25 +02:00
d1e3993bd0
kcu105: daq2 updates
2014-10-27 09:59:56 -04:00
d471b61f3e
fifo: merge zynq and non-zynq
2014-10-27 09:59:54 -04:00
Adrian Costina
Rejeesh Kutty
Istvan Csomortani
Michael Hennerich