530aca9754
daq2: Parameterize JESD204 configuration values
...
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-20 12:54:03 +02:00
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
...
Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
a589753d92
project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
2019-06-29 06:53:51 +03:00
43725429ac
adi_project: Rename the process adi_project_xilinx to adi_project
2019-06-29 06:53:51 +03:00
b7ca17f02b
scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects
2017-06-07 12:06:50 +03:00
edd5e9570f
file renamed; sed output; fingers crossed
2017-02-22 15:56:37 -05:00
73413366bc
daq2/all - warnings fix
2016-08-17 10:36:00 -04:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
6862655b0d
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
7fba7cc6e5
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
39cc7b8b2e
daq2_zc706: Add constraint file for the PLDDR
2014-12-18 10:00:35 +02:00
20d59ce39b
daq2: dma fifo modifications
2014-10-22 16:39:28 -04:00
f94cbbb0aa
daq2: register map updates
2014-07-03 12:36:37 -04:00
7efd6149f8
daq2: initial checkin
2014-06-12 15:54:25 -04:00
Dan Hotoleanu
Adrian Costina
Istvan Csomortani
Rejeesh Kutty
Lars-Peter Clausen