We need to make sure to not prematurely de-assert the s_valid signal for the
request splitter when disabling the DMAC. Otherwise it is possible that
under certain conditions the DMAC is disabled with a partially accepted
request and when it is enabled again it will continue in an inconsistent
state which can lead to transfer corruption or pipeline stalls.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
All components should use the internal 'do_enable' signal instead of the
external 'enable' signal. The former correctly incorporates the shutdown
sequence and does not get asserted again until the shutdown has been
completed. Using the external signal can cause problems when it is disabled
and enabled again in close proximity.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently when the DMAC gets disabled the request_generator will still
generate all remaining burst requests for the currently active transfer.
While these requests will be ignored by the source and destination component
this can still take a fair amount of time for long transfers.
So just stop generating burst requests once the DMAC is being disabled.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Refactor the fifo_inf modules to always correctly generate the underflow and
overflow status signals. Before it was possible that in some cases they
were not generated when they should have been.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This silences warnings from the tools about having no clock assigned to the bus.
Also fix the name of the TVALID signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The dummy a{r,w}len fields should have the same width as the real a{w,r}len
fields in order to not break auto AXI bus version detection.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Clear the pipeline when no transfers are active to make sure that we do not
get residual data on the first sample for the next transfer.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
We can remove the Altera toplevel wrapper if we switch the axi4 control bus
to axi4lite and add the few missing signals that are required by the Altera
interconnect to both the control and the data buses.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
We must make sure that the response ID is the same as the request ID when we
accepted the request. Otherwise we might respond with the wrong ID and the
system will lockup.
Also set rlast to 1 instead of 0.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Make sure that the address generator behaves correctly when the buswidth is not
64-bit. Also since the source and destination can have different widths add
separate parameters for source and destination address alignment.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
We do not know which 'last' condition to use before hand, but we can pre-compute
the result for both conditions and then use them. This removes the comparison
from the already pretty long combinatorial path.
Also simplify a few expressions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The read data also becomes available only with a delay of one clock cycle,
sending the ack too early will result in bogus register reads.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
During an ID sync the request_id might increment, we should not generate a
response in this case. Since the ID sync only happens when the core is disabled
check that the core is enabled before generating a response.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The pending_burst signal and the expression id != request_id are almost
identical. pending_burst goes high with a delay of one clock cycle, but the
important thing is that it goes low on the same clock cycle as the expression.
By using pending_burst here instead of 'id != request_id' we can reduce the
fanout of the 'id' register and improve the timing of the core.
Lars-Peter Clausen
Adrian Costina
Rejeesh Kutty