- allow specifying the name of Axi Lite interface from the peripheral were to connect the control bus
- some DDR controllers have an Axi Lite control interface, this creates
a second address segment which causes issues, differentiate the memory
segment from control registers segment
The 2020.1 Xilinx tools have a different tcl procedures to build the boot.bin
file.
This commit updates the adi_make tcl flow for the new tools. The new
process is not backwards compatible with tools older than 2020 version.
In order to workaround optimization issues hit in Vivado 2020.2,
set ADI_USE_OOC_SYTHESIS variable by default to 1. This will build
projects in Out Of Context mode.
Projects can be build in Project Mode by exporting ADI_USE_OOC_SYTHESIS=n.
Update vivado version to 2020.2:
- update default vivado version from 2020.1 to 2020.2
- add conditions to apply specific contraints only in Out Of Context mode.
- update DDR controler parameters for vcu118 and kcu105 dev boards
The goal of this commit is to make sure there isn't any significance to
the order in which parameters of ad_connect are specified.
As an example, previously you could only `ad_connect target VCC`, while
`ad_connect VCC target` would fail.
Note: This code intentionally ignores bd_{,intf_}ports, because
these can all be treated as bd_pins.
Signed-off-by: David Winter <david.winter@analog.com>
This will allow building base test harnesses and place on top of them
existing block designs for simulation purposes.
Test harnesses will contain basic functionality like
- clock and reset generators
- AXI master to aid register access of the cores.
- memory model of the DDR
- interrupt controller
Existing procedures (ad_mem_hp0_interconnect, ad_cpu_interconnect, ... ) will
connect to this harness as they do to a real base design.
To support deterministic latency with non-power of two octets per frame
(F=3,6) the interface width towards the transport layer must be resized
to match integer multiple of frames.
e.g Input datapath width = 4; Output datpath width = 6;
for F=3 one beat contains 2 frames
for F=6 one beat contains 1 frame
The width change is realized with a gearbox.
Due the interface width change the single clock domain core is split
in two clock domains.
- Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b
- lane rate / 20 for input datapath width of 8 octets 8b10b
- lane rate / 66 for input datapath width of 8 octets 64b66b
- Device clock : Link clock * input data path width / output datapath width
Interface to transport layer and SYSREF handling is moved to device clock domain.
The configuration interface reflects the dual clock domain.
If Input and Output datapath width matches, the gearbox is no longer
required, a single clock can be connected to both clocks.
In most of the standalone projects the generic project creation flow is not followed. The project's device
is defined manualy. This fix makes sure that those projects still builds without an issue.
NOTE: In these case we should use adi_project_create directly in system_project.tcl.
Morten Jensen
Filip Gherman
LIacob106
Laszlo Nagy
hotoleanudan
Adrian Costina
stefan.raus
Robin Getz
sergiu arpadi
AndreiGrozav
David Winter
vladimirnesterov
Istvan Csomortani
aholtzma
Stanca Pop