Commit Graph

59 Commits (0c2745361ba5bee090619bb09f2be230b6444c3b)

Author SHA1 Message Date
Adrian Costina 41e717ec2c adrv9009: Added option for enabling the second observation channel 2018-06-29 11:10:39 +03:00
Adrian Costina e982232d75 adrv9009: Increased DMA clock frequency to ~333 MHz, by enabling AXI SLICES for DMAs 2018-06-12 23:53:56 +03:00
Adrian Costina f3ac5d3ad3 adrv9009: Increase all DMAs MAX_BYTES_PER_BURST to 256 2018-06-12 23:53:56 +03:00
Adrian Costina 801351d93c adrv9009: Increase sys_dma_clk to 325MHz. At 333 MHz, there are timing violations 2018-06-12 23:53:56 +03:00
Adrian Costina cc18f76e3b adrv9009: Reduced DAC FIFO size, as it's not useful for real applications and the memory can be used in other parts of the design 2018-06-12 23:53:56 +03:00
Adrian Costina 65c765eb33 adrv9009: Increase DMA FIFO sizes 2018-06-12 23:53:56 +03:00
Adrian Costina 4999a52f87 adrv9009: Removed ZC706 based project 2018-05-14 11:36:31 +03:00
Adrian Costina e445fbe04f adrv9009: Improved data throughput and DAC FIFO size
Moved XCVR related connections to HP0, where the HP shares the MUX with the Video DMA
HP1 and HP2 are used for RX OS and RX DMAs, sharing the MUX. Usually they shouldn't run at the same time.
HP3 is used for TX DMA, sharing the MUX with the FPD DMA controller
All HPx and DMA buswidths have been increased to 128 bits
The HPx-DMA clock has been increased to 300 MHz
DAC FIFO address size has been increased to 17
2018-05-14 11:33:04 +03:00
Adrian Costina e4d579726d Renamed ad9379 to adrv9009 2018-04-26 18:19:11 +03:00