When using an oversampling of 2 for axi_dac_interpolate the rate was
the same as with oversampling by 1(bypassing).
This commit removes the bypass for the ratio of 2.
For projects where the clock ratio between the sampling clock and core clock
is higher than 2, the ad_dds generates a number of samples equal with
the clock ratio. There is a phase offset between the samples, proportional
with the requested DDS frequency.
In scenarios where the DDS out frequency is closer to the upper
limit(Nyquist) and/or the clock ratio is also greater than 2 and the
dac_data_sync reminds low for an extended period of time, the DAC will
receive at each core clock period, a number of samples equal with the
clock ratio and with an amplitude influenced by the DDS out frequency.
In most cases similar with a sawtooth signal.
With this commit we ensures that samples received by the DAC are 0 for
the period where dac_data_sync signal is high. Only when the signal
transitions to low, the phase accumulator is initialized and the phase
information is passed to the phase to amplitude converter.
Another issue can appear when the sync signal is too short; less then
CLK_RATIO * clock cycles. Because the phase accumulator will not
synchronize at all stages, the final result will be a random combination of
sine-waves. Added a minimum sync pulse after the dac_data_sync is set
low.
When frame alignment error monitoring is enabled and error threshold is met
at least for one lane, generate an interrupt so software can reset the link and
do further bring-up steps.
Add support for RX frame alignment character checking when scrambling is enabled and
for link reset on misalignment.
Add support for xcelium simulator to jesd204/tb
The Pattern generator is part of the axi_logic_analyzer core.
The trigger signal can be internal (Oscilloscope or Logic Analyzer) or
external(TI or TO pins).
The sdo_enabled and sdi_enabled control lines are generated from the
current state of the CMD bus.
In case of a delayed SDI latching the sdi_enabled can be deasserted at
the moment of the last valid bit, losing the generation of the sdi_data_valid
signal, which eventually cause a data loss, or even deadlock on software driver.
To make the logic mode robust, latch the value of the CMD[9:8] at every
transfer command. Doing so the sdo_enabled and sdi_enabled control lines will
store the last active transfer command state and they will be
independent of the current state of the CMD bus. This way we can add
longer time delay to the SDI latching if it's necessary.
Having the same name for dac and adc TPLs creates conflict in the
address segment naming having random names associated to the segments.
This causes difficulties during scripting of the project in test bench
mode.
The value of the HDL parameter NUM_OF_SDI can be read out from the
register at address 0x0C. The same register contains the value of the
DATA_WIDTH.
The register has the following bit layout:
[15: 0] DATA_WIDTH
[23:16] NUM_OF_SDI
[31:24] 8'b0
Forward the offload's sync_id to the register map, by defining an
additional AXI stream interface between the offload and axi_spi_engine.
The last sync_id of the offload module can read out from the
register 0x00C4. It also can generate and interrupt if the irq mask is
configured accordingly.
There is a major compatibility issue between 2019.1 and 2019.2.
The file system_top.hdf got a different file extention. This will
cause a compilation failer in the end of the build. To save time
and fail earlier, upgrade the version mismatch message to ERROR.
If user still wants to build a branch with different tool version
the variable ADI_IGNORE_VERSION_CHECK should be set to 1.
The external synchronization signal should be synchronous with the
dac clock. Synchronization will be done on the rising edge of the signal.
The control bit is self clearing. Status bit shows that the synchronization
is armed but the synchronization signal has not yet been received
Added EXT_SYNC parameter to be able to keep the dac_sync original
behavior
The external synchronization signal should be synchronous with the
adc clock. Synchronization will be done on the rising edge of the signal.
The control bit is self clearing. Status bit shows that the synchronization
is armed but the synchronization signal has not yet been received. While
the synchronization mechanism is armed, the adc_rst output signal is set
The current format should allow for the SYSREF signal to be used as
synchronous capture start, but will need to be disabled before the
synchronization mechanism is armed
The commit 9ab88f1200 introduced a new
feature for the execution module, which provides the possibility to
delay the SDI line latch with one or more core clock cycle. Unfortunatly
the implementation was not correct and the SDI line was latched at the
wrong time.
This patch fix the aligment of the shift register and the SDI_DELAY parameter,
to latch the SDI line of the physical interface at the right time.
Improve the description of the feature.
On the Xilinx PHY the available PLL options depends on the lane rate.
Encoding is:
0 - CPLL
1 - QPLL0
2 - QPLL1
Since the selection of line rate is available from the project also the
PLL selection must be exposed.
AndreiGrozav
Laszlo Nagy
Matt Blanton
Istvan Csomortani
Stanca Pop
Arpadi
Adrian Costina