Import documentation from the IP library and wiki page.
Make the background of the clock images less opaque so it's easier to
read.
Don't split roles, even though are valid, are a nightmare to
regex-match, if necessary.
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
SPI Engine: create inverted CS mode
Add a CS Invert Mask instruction for selecting the polarity of
the Chip Select pins.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Rename "idle bus" to "bus available" per specification:
* Tune it to require < 1us.
Rename "IBI auto" to "IBI listen":
* Clarify that the controller is listening for IBI's:
* Explain that this field should be set.
* Fix for known IBI's DA with IBI disabled.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
New features:
1. External sync force the phase align. The external sync was used to align
the phases of enabled pwms, but only after being armed by a
load_config signal toggle.
This feature lets the user decide between using load_config to
arm and wait for a neg-edge of sync or automatic phase align trigger
on the ext_sync neg-edge.
2. Force align. Lets the user chose between immediately stopping the
active pulses and realigning them, or waiting for all running pulse
periods end, before realigning.
3. Start at sync. When this feature is activated, the pulses will start immediately
after the trigger event. Otherwise, each pulse will start after a period
equal to the one for which it is set.
4. Use parameters to set the default status after reset of the
- soft reset
- start at sync
- force align
- ext sync align
Update regmap.
Fixes:
1. The polarity on disabled channels was staying high instead of low.
2. Fix 0 and 100 proc duty cycle configuration.
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
Signed-off-by: Alin-Tudor Sferle <Alin-Tudor.Sferle@analog.com>
docs: Add JESD204 documentation in sphinx
Fixes several semantic issues from the original doc in wiki
Implicit path to library when the doc is hierarchically coherent with the
library.
Signed-off-by: Carlos Souza <carlos.souza@analog.com>
Co-authored-by: Jorge Marques <jorge.marques@analog.com>
* SPI Engine: Add registers for Offload memory and FIFO sizes
Adds registers at dword 0x04 and 0x05, respectively allowing software
to get the sizes of the Offload Module memories (command and sdo) or
the sizes of the FIFOs on the AXI regmap.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Drop part role, use generic adi instead for root adi domain links.
For future reference, the snipped used was:
find ./docs/projects -type f -exec sed -i 's/:part:/:adi:/g' {} \;
Drop Containerfile.
Add option to validate links status (e.g. 200, 404), intended mostly for CI
use to check if a page has disappeared from the internet.
Validate links uses coroutines to launch multiple tasks concurrently,
but do it in bundles to avoid being rate limited.
Fixup regmap styling.
Add imoldovan, jmarques, spop, lbarbosa as docs codeowners.
Remove branch field for links to the hdl repo.
Change git role to display full path.
Fixup ZedBoard link label, remove IP List, add SYSID_ROM dokuwiki link
in ad716_sdz project.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
-Updated description of some fields of these registers: REG_CHAN_CNTRL_1,
REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4,
and REG_USR_CNTRL_5
-Added two new registers, both with their own fields and description:
REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10
Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
Automate table generation for register maps.
Based on tfcollins' vger python scripts.
There are docs/adi_regmap_*.txt with more than one regmap per file,
so the logic changed to allow that.
Using title tool as the unique identifier now.
It has a global option to set the default state (hidden or visible)
for the collpasible tables.
Also remove CSVs.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
docs/regmap/adi_regmap_adc.txt:
- add softspan to regmap
library/common/up_adc_channel.v
- update copyright year header
- add softspan to regmap
library/common/up_adc_common.v
- update minor version
Signed-off-by: John Erasmus Mari Geronimo <Johnerasmusmari.Geronimo@analog.com>
Alin-Tudor Sferle
podgori
PopPaul2021
Jorge Marques
LBFFilho
Ionut Podgoreanu
AndreiGrozav
Jorge Marques
Stanca Pop
caosjr
Alin-Tudor Sferle
Iulia Moldovan
PopPaul2021
Cristian Mihai Popa
Jem Geronimo
Travis F. Collins
Filip Gherman