Commit Graph

5 Commits (0c614bab51a7c43f26bd885723f30970f8f6ff77)

Author SHA1 Message Date
Jorge Marques 8e32f0e21d
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 10:05:12 -03:00
LBFFilho e757859b56
SPI Engine: create inverted CS mode (#1301)
SPI Engine: create inverted CS mode

Add a CS Invert Mask instruction for selecting the polarity of
the Chip Select pins.

Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
2024-05-08 11:19:37 -03:00
Stanca Pop 4d587b2c0e regmap: Update SPI Engine regmap 2024-03-27 16:58:20 +02:00
LBFFilho 2052817dcb
SPI Engine: Add registers for Offload memory and FIFO sizes (#1279)
* SPI Engine: Add registers for Offload memory and FIFO sizes

Adds registers at dword 0x04 and 0x05, respectively allowing software
to get the sizes of the Offload Module memories (command and sdo) or
the sizes of the FIFOs on the AXI regmap.

Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
2024-03-08 08:40:48 -03:00
PopPaul2021 542c361e0a
docs/regmap: Added ADI regmap_*.txt files (#1008) 2022-09-21 15:12:35 +03:00