* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
For consistent simulation behavior it is recommended to annotate all source
files with a timescale. Add it to those where it is currently missing.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This module upscale an n*sample_width data bus into a 16 or 32*n data
bus. The samples are right aligned and supports offset binary or two's
complement data format.
Iulia Moldovan
Istvan Csomortani
Lars-Peter Clausen