Iulia Moldovan
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68461110aa
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Replace link in license header from master to main
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
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2024-01-16 16:48:45 +02:00 |
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Iulia Moldovan
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c9a7d4d927
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Add copyright and license to .tcl, .ttcl files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
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2023-07-25 15:22:26 +03:00 |
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Iulia Moldovan
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1cac2d82e1
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Add copyright and license to .xdc files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
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2023-07-25 11:03:02 +03:00 |
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Iulia Moldovan
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28c06d505f
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Add/edit copyright and license for .v, .sv files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
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2023-07-11 15:17:41 +03:00 |
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Iulia Moldovan
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db94628cc6
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library & projects: Update Makefiles
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
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2023-01-27 11:54:05 +02:00 |
laurent-19
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1eb5f4985b
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projects/common: Add build files templates carriers. Modified Quartus Versions
The build files are available for the following carriers:
* intel: a10gx, a10soc, c5soc, de10nano, s10soc
* xilinx: coraz7s, kc705, kcu105, vc707, vc709,
vck190, vcu118, vcu128, vmk180,
zc702, zc706, zcu102, zed
* Added Makefiles, system_constr.sdc, system_qsys intel
* Added Makefiles, system_bd, system_constr xilinx
* de10nano, c5soc: Changed quartus version from 20.1.1 to 21.1.0
according to last commit update
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
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2022-10-05 10:47:21 +03:00 |
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laurent-19
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6b94259a52
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projects/common: Add system_top _project templates
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Correct code and modify according to guidelines
* Added spacing to ports declaration
* Corrected coding mistakes/misspelling
* Modified/added variables names
* Added seetings (intel) and removed specific optimization settings
* Added assignments to unassigned pins (gpios)
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Correct/Add missing wrapper ports and iobufs
* Added port in wrapper (mainly spi) according to base design file
* Added instances of iobufs where missing
* Corrected gpio assignments or added missing ones
* Corrected minor guidelines mistakes
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
ac701/system_top.v: Change top based on previous projects
* Looked at fmcomms1, fmcomms2 from hdl_2016_r1 and datasheet
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
projects/common: Modify templates to build without errors
* Changed path for adi_env.tcl
* Moved adi_project command before assign intel
* Removed unnecessary spi signals
* Added spi ports with default logic
* a10soc: Removed pl-ddr signals and ports
* ac701: system_bd: Modified mdio interface
system_project: Added adi_board, adiobuf sourcing
system_top: Removed hdmi, i2c, fanpwm, spdif ports
according to base design
* c5soc: Added version settings
Removed unused gpios
* microzed: system_bd: Enabled RTS1 to use FCLK
system_top: Removed hdmi, i2c, unused gpios
* vc709: Separated input from ouput gpio, according to bd
Removed unnecessary ports
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Delete microzed vmk_es templates
* Removed hp0 interconnect from cora base design
* Added extra line to files de10nano
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
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2022-09-20 17:00:49 +03:00 |
AndrDragomir
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72cf8f9b5d
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projects/common: Add fmc connection files for every platform
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2022-09-20 14:11:08 +03:00 |
hotoleanudan
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1bc8a41aea
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vc709_carrier: Add vc709 carrier (#788)
Added vc709 carrier to the projects/common folder location.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
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2021-11-02 12:05:42 +02:00 |