This commit adds a new synthesis option to the design, that controls
whether an internal clock domain crossing will be generated. Disabling
this option allows you to use a synchronization signal that is
synchronized to the write clock domain externally, and possibly shared
between multiple devices.
The default value retains the old behavior.
Signed-off-by: David Winter <david.winter@analog.com>
Add CMOS support for the interface for the following symbol modes on Xilinx devices:
A B C D E F G H
CSSI__1-lane 1 16/8 80(SDR)/160(DDR) 80 - SDR/DDR SDR/DDR->4/2(C=16), 2/1(C=8)
Columns description:
A - SSI Modes
B - Data Lanes Per Channel
C - Serialization factor Per data lane
D - Max data lane rate(MHz)
E - Max Clock rate (MHz)
F - Max Sample Rate for I/Q (MHz)
G - Data Type
H - DDS Rate
CSSI - CMOS Source Synchronous Interface
This commit changes the transfer length register to work in increments of
64 bytes and without offset. The true transfer length can now be
determined by multiplying the value of the transfer_length register with
64.
A value of zero is interpreted as a request for all available storage.
Additionally, this commit fixes an off by one issue that was discovered
during testing of the RX path.
Signed-off-by: David Winter <david.winter@analog.com>
Update vivado version to 2020.2:
- update default vivado version from 2020.1 to 2020.2
- add conditions to apply specific contraints only in Out Of Context mode.
- update DDR controler parameters for vcu118 and kcu105 dev boards
The width of the parameter `device_cfg_octets_per_multiframe` doesn't match the width in the submodules and corresponding slave module jesd204_tx, resulting in a warning generated during validation in Vivado. This patch increases the width of this parameter in axi_jesd204_tx.
Fix offset for pwms with different periods.
The previous version was using an offset scheme based on pwm counter_0.
By using a separate offset counter the user will not be constrained by
pwm_0 period in regards with the offset of other pulses. In this version
offset 0 is used to delay pwm 0 in regards to the offset counter.
The offset counter will start after the load_config signal is asserted
and all active pwm counters finish the previous cycle or by a software
reset.
The software reset should also be used when using external_sync.
* fixes DRC warning that the clocking configuration may result in data errors
* fixes ioserdes reset issue with synchronous de-assert in data clock domain
This commit adds a standalone TDD IP core based on the
existing up_tdd_cntrl module and the up_axi pcore <-> axi bridge.
Signed-off-by: David Winter <david.winter@analog.com>
If all channels are selected for read the values and ready signals from every
transceiver are combined. Each element merges his signals with the previous.
The first element of the chain must assume the previous channel is always ready.
This reverts commit 829e4155ca.
The first element of the read chain must assume there is no valid element
in front of it. For each element the ready signal of the transceiver should be
routed if the channel is selected either by channel number or broadcast.
When the current element is not selected it should forward the ready signal from
the previous element, however this is not the case for the first one.
Having a constant 1'b1 connected to the ready input of the first element
corrupts the first read of the first channel after a channel switch.
This change will break broadcast reads.
Adds a magic identification value of 0x54444443 at word address 0x3.
It is derived from the ASCII String "TDDC" interpreted as a big-endian
32-bit unsigned integer.
Signed-off-by: David Winter <david.winter@analog.com>
For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock
that is 2x of the CLKUSR2 (lane rate/66),
CLKUSR = 2 x CLKUSR2
CLKUSR = lane rate / 33
This can be driven from the GT reference clock or second out clock div2.
This commit also:
- fix eyescan scale on GTY
- remove irrelevant parameters
If R1 mode is first syncronized to the dac clock domain will prevent its
usage if the dac clock is missing. In such case the synchronization will not
propagate.
Depending on FPGA technology the physical layer uses different
deserialization factors and corresponding clock division factors to
divide the source synchronous interface clock. This must be
exposed to software so it can act on it while setting the DDS rate.
Xilinx CMOS clock ratio - 4
Xilinx LVDS clock ratio - 4
Intel CMOS clock ratio - 1
This module creates sync header alignment described in section 7.6.1 of
the JESD 204C specification.
The alignment relies on the bitslip capability of the connected
transceiver.
Create a common 'run_tb.sh' script to be called by every testbench.
Unify file and testbenches names.
Fix util_pack/cpack_tb.
Add parameters '-batch' and '-gui' for modelsim and xsim simulators (default is gui)
Add ascript for that generates output in xml format (used by CI tools).
get_cell on i_lmfc/cdc_sync_stage1_reg doesn't return anything because design was updated.
This generates a CRITICAL WARNING and since the constraint it not necessary anymore, it can be deleted.
If Tx source synchronous clock is not routed through clock capable pins
the interface and driving logic must run on the Rx interface clock.
This introduces a dependency, Rx interface must be bring up before the
Tx. In this mode a Tx only operation is not possible.
This is done through a synthesis parameter.
Expose this parameter to the software so it can query if the limitations
exists in the implementation.
If the REMOVE_NULL_BEAT_EN is set, in FIFO mode, all the beats with a
NULL TKEEP will be removed from the AXI stream.
This feature is used initially in data_offload, to create a continues and
cyclic TX data stream for DACs, when the IPs in the path have different data
widths.
Robin Getz
David Winter
Iacob_Liviu
Filip Gherman
alin724
Laszlo Nagy
stefan.raus
Istvan Csomortani
Nick Pillitteri
Isaac T
AndreiGrozav
Josh Blum
Alin-Tudor Sferle