Commit Graph

5841 Commits (0d9e38bdbe32f0a4f7981a7adcefb60936ce0a95)

Author SHA1 Message Date
Adrian Costina 9364c8501a adrv9009_zu11eg: Add synchronization at application layer
Switch RX path reset to be controlled by the TPL and use
RX SYSREF as external synchronization for the ADC TPL
Use TX SYSREF for synchornizing the TX DDS
2020-10-07 09:04:21 +03:00
Laszlo Nagy 4026eaa19b ad9081_fmca_ebz: Fix device clocks termination
The device clocks are AC coupled LVDS lines without external termination.
For proper operation internal differential termination must be enabled,
the DQS_BIAS will DC bias the AC coupled signal to VCCO/2 (1.8/2) 0.9V
2020-10-06 16:13:21 +03:00
hotoleanudan 1c208c01d6
ad9656:Add reference design for the ad9656 eval board (#494)
Added reference design for the ad9656 evaluation board coupled with the
zcu102 carrier board. The JESD204 communication link that transfers data
from the 4 ADCs to the FPGA has the following paramenters : L=4, M=4, S=1,
F=2, HD=0, N=16, NP=16. The JESD204 line rate is configured to be 2.5GHz.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2020-10-06 09:53:40 +03:00
sergiu arpadi 23cd6d2f91 sysid: Remove cstring init string
These two projects were originally missed by the find/replace command
2020-10-02 23:34:40 +03:00
Sergiu Cuciurean da6d9da4f0 projects: cn0540: coraz7s: Add XADC support
The coraz7s has an Arduino/chipKIT Shield connector with 6 Single-ended
and 8 Differential Analog inputs tied to Xilinx's XADC.
The CN0540 uses the A0-5 pins as single-ended ADC channels to monitor
the differential input, ADC driver, and buffer voltages.

Signed-off-by: Sergiu Cuciurean <sergiu.cuciurean@analog.com>
2020-10-02 11:14:21 +03:00
Istvan Csomortani 11822e2824 cn0540/coraz7s: Set and input delay of one spi_clk cycle for the MISO line
Note, the current SCLK to spi_clk ratio is four. That means, the input
delay in the MISO line is 25% of the SCLK period.

If the SCLK to spi_clk ratio is changing, this constraint must be
updated.
2020-10-02 10:50:06 +03:00
Istvan Csomortani dae1de0405 cn0540/bd: Generate a 80MHz spi_clk
Generate a higher frequency of spi_clk using an axi_clkgen. (MMCM)

CAUTION: ad7768-1 is still violating the standard SPI timing,
reducing the timing window significantly for the last bit (or last high
bit).
2020-10-02 10:50:06 +03:00
Sergiu Arpadi 681ddc2e25 axi_gpreg: Add ttcl for clock_mon constraints
fixed critical warnings generated when the NUM_OF_CLK_MONS parameter
is set to 0 and the constraints written in up_clock_mon_constr.xdc
cannot be applied; removed up_clock_mon_constr.xdc from ip core.
2020-10-01 16:10:55 +03:00
Sergiu Arpadi c656a2e29b sysid: Initialize parameter 2020-09-30 19:12:24 +03:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Laszlo Nagy e759c1855b jesd204: Clean-up combinatorial logic
To correctly model combinatorial logic in always blocks
blocking assignments must be used.
2020-09-29 17:27:42 +03:00
Laszlo Nagy 7c523fbf02 jesd204_rx: Reset frame alignment monitor event generator
If the link is not enabled no event should be generated.
2020-09-29 17:27:42 +03:00
Laszlo Nagy 0ecf4254ec axi_jesd204_rx: Ignore events if link not enabled
When the link is disabled the events can be ignored.
This is required by the free running event counter that can catch
invalid events during startup cased for example by an invalid link clock.
2020-09-29 17:27:42 +03:00
Laszlo Nagy aa4de79045 jesd204/jesd204_rx: Ignore frame alignment errors if lane is not in DATA phase
If the lane looses synchronization due invalid characters or disparity
error the lane alignment monitor checks random input which results in
irrelevant reporting of frame alignment error.
2020-09-29 17:27:42 +03:00
Laszlo Nagy d825fffd62 jesd204/jesd204_rx: Reset error counter once all lanes synced
If all lanes are synchronized (CGS state machine is in DATA phase) for long
enough therefore the link is also synchronized/DATA phase reset the error
counter since the accumulated values during INIT/CHECK are irrelevant.
These errors are handled by the per-lane CGS state machine.

All errors accumulated during INIT/CHECK phase of CGS are relevant only
if the link is unable to reach the DATA phase.
The link stays in DATA phase unless software resets it,
so all errors accumulated during the DATA phase are relevant.
2020-09-29 17:27:42 +03:00
Laszlo Nagy ee143d80d6 jesd204_rx/jesd204_rx_ctrl: Fix de-glitch mechanism
The previous implementation of the de-glitch only delayed the assertion
of the SYNC phase by 64 clock cycles with the DEGLITCH state but if meanwhile
one of the lanes got into a bad state cgs_ready de-asserted the state machine
continued to go SYNCHRONIZED (DATA) state.
This change extends the required number of consecutive cycles while all lanes
must stay in data phase before moving the link to SYNCHRONIZED state from 8 to 256;
This increases the reliability of link bring-up without needing extra
link restarts from software side.
2020-09-29 17:27:42 +03:00
Laszlo Nagy 5edc798b6b axi_jesd204_common/jesd204_up_common: Add event stats
Add statistics for :
 - number of link enable events
 - number of interrupt events (regardless of mask)

0x0B0 0x2C0 Stats Control Register
  [0] - Write 1 to clear stat registers

0x0B1 0x2C4 Link Enable Stat Register
  [15:0] Number of times the link was enabled from power-on or from last
         stat clear

0x0B4 0x2D0 IRQ Stat Register 0
  [31:16] IRQ 1 counter
  [15:0]  IRQ 0 counter

0x0B5 0x2D4 IRQ Stat Register 1
  [31:16] IRQ 3 counter
  [15:0]  IRQ 2 counter

0x0B6 0x2D8 IRQ Stat Register 2
  [31:16] IRQ 5 counter
  [15:0]  IRQ 4 counter

0x0B7 0x2DC IRQ Stat Register 3
  [31:16] IRQ 7 counter
  [15:0]  IRQ 6 counter
2020-09-29 17:27:42 +03:00
Sergiu Arpadi 33f612091b spi_engine: Add spi_engine.tcl 2020-09-25 16:41:33 +03:00
Sergiu Arpadi bd2126fd2f cn0363: Remove iobuf for spi sdo
iobuf was generating drc warning because it was not fully connected.
2020-09-25 16:40:41 +03:00
Istvan Csomortani 9c827d6b03 cn0540/de10nano: Ignore 15003 critical warning
Ignore the following critical warning on DMAC instance:

Critical Warning (15003):  "mixed_port_feed_through_mode" parameter of RAM atom
system_bd:i_system_bd|axi_dmac:axi_dmac_0|axi_dmac_transfer:i_transfer| \
dmac_request_arb:i_request_arb|dmac_dest_mm_axi:i_dest_dma_mm| \
altsyncram:bl_mem_rtl_0|altsyncram_0tp1:auto_generated|ram_block1a1
cannot have value "old" when different read and write clocks are used.
2020-09-25 12:56:53 +03:00
Istvan Csomortani 1b713d8265 axi_hdmi_tx: Update register initialization
Quartus Standard 19.1 throw a critical warning for registers that have
different reset and initial power-up level.

Do not initialize those registers so we can get rid of the warning.
2020-09-25 12:56:53 +03:00
Istvan Csomortani 9cac38017b daq2/a10soc: Set optimization mode to high performance effort 2020-09-25 12:56:14 +03:00
Istvan Csomortani 230c579339 common/s10soc: Input ports do not have a current strength property 2020-09-25 12:56:14 +03:00
Istvan Csomortani 5644907f75 adi_intel_msg: Dissable "unused TX/RX channel" critical warning for Stratix 10 2020-09-25 12:56:14 +03:00
Stanca Pop a738879fa0 ad77681evb: Remove redundant ad_data_clk 2020-09-25 12:20:41 +03:00
Adrian Costina 144fcc2965 adrv9009: Fix typo for number of samples calculation for observation channel 2020-09-25 11:58:58 +03:00
Adrian Costina bde2d1d66d fmcomms8: zcu102: Leave the SPI constraint at 25 MHz 2020-09-25 11:54:12 +03:00
Adrian Costina 4d2e05d5dd fmcomms8: common: In the SPI module, use ad_iobuf instead of a Xilinx primitive 2020-09-25 11:54:12 +03:00
Adrian Costina f8c2eb12d4 fmcomms8: zcu102: Remove the test pins, as they are not connected 2020-09-25 11:54:12 +03:00
stefan.raus d2ef1bcef5 library/commmon: Fix data width warnings
ad_tdd_control.v: Set ON and OFF local parameters on just one bit.
up_dac_common.v: Set CLK_EDGE_SEL parameter on just one bit.
2020-09-23 09:16:48 +03:00
stefan.raus 1e31b9dd97 arradio: Remove unused signals
Remove 'ad9361_clk_out' since is not used anymore, fixing in this way 'Warning (21074): Design contains 1 input pin that do not drive logic'
2020-09-23 09:16:48 +03:00
sergiu arpadi f2f6422751 sysid: Fix board/project name underscore issue 2020-09-17 10:32:58 +03:00
AndreiGrozav 6ae822d42c cn0506_rmii: Fix no defined clock warnings 2020-09-16 10:57:15 +03:00
Istvan Csomortani 49d4286459 cn0540/de10nano: Delete GPIO connection to DRDY 2020-09-15 18:14:23 +03:00
Istvan Csomortani 4838ac0ac2 cn0540/coraz7s: Time the SPI interface of AD7768-1 2020-09-15 18:14:23 +03:00
AndreiGrozav 0933949ad7 adv7513: Add initial project for de10nano 2020-09-15 18:14:23 +03:00
Stanca Pop 043ddbaf9f cn0540: Add de10nano reference design 2020-09-15 18:14:23 +03:00
Istvan Csomortani ad8d2d225f de10: Delete redundant base design 2020-09-15 18:14:23 +03:00
Stanca.Pop fd1c3c7cdd common/de10nano: Add de10nano base design 2020-09-15 18:14:23 +03:00
Stanca Pop 6cea8ce777 adi_project_intel: Add de10nano support 2020-09-15 18:14:23 +03:00
Istvan Csomortani cba3c0f4f1 spi_engine_offload: Define status_sync interface 2020-09-15 18:14:23 +03:00
Istvan Csomortani 780579f3e9 spi_engine_offload: Delete trailing whitespaces 2020-09-15 18:14:23 +03:00
Istvan Csomortani b827322917 spi_engine_execution: Add missing parameter definition into hw.tcl script 2020-09-15 18:14:23 +03:00
Istvan Csomortani f67209e125 axi_spi_engine: Fix the hw.tcl script
Define both AXI4 Memory Mapped and microprocessor interface for the
reigster map, then activate/deactive one of it in fucntion of the memory
interface type parameter.

Define the missing status_sync interface, which should be connected to
the offload.
2020-09-15 18:14:23 +03:00
Istvan Csomortani f934ff7e4e axi_spi_engine: Add missing ports to every sub-module instance 2020-09-15 18:14:23 +03:00
Istvan Csomortani a5326cb3d2 axi_spi_engine: Refactoring sdi_fifo read outs
Context switching with a parameter is not a good idea. The simulator
may evaluate both branch of the IF statement, even though the inactive
branch may not be valid.

Use if..generate to make the code more robust for both synthesizers and
simulators.
2020-09-15 18:14:23 +03:00
AndreiGrozav 422d7c949c axi_hdmi_tx_vdma: Use only synchronous reset 2020-09-15 18:14:23 +03:00
AndreiGrozav 520a7ea972 axi_hdmi_tx: Update IP to latest HDL flow
Conflicts:
	library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl
2020-09-15 18:14:23 +03:00
AndreiGrozav 585ed44983 Add 'SE Base' family to the supported FPGAs 2020-09-15 18:14:23 +03:00
Istvan Csomortani 40772a8b2c ad40xx_fmc/zed: Fix constraints, to avoid critical warnings in synthesis 2020-09-15 13:08:39 +03:00