5df2961624
ad_mux: another fix cases where channel number is not power of mux size
2020-11-27 09:45:11 +02:00
0badfdfa31
ad_mux: fix cases where channel number is not power of mux size
2020-11-27 09:45:11 +02:00
3dd370a27c
ad9081_fmca_ebz: enable xbar in DAC TPL
2020-11-27 09:45:11 +02:00
01f4576fcd
ad_ip_jesd204_tpl_dac: added xbar for user channels (dma data)
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Allow channels received from dma to re-map to other channels, e.g. allowing
broadcasting the same channel to all channels.
The feature is selectable with synthesis parameter and disabled by default.
2020-11-27 09:45:11 +02:00
5c561665b0
common/ad_mux: Pipelined mux, rtl and TB
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Build a large mux from smaller ones defined by the REQ_MUX_SZ parameter
Use EN_REG to add a register at the output of the small muxes to help
timing closure.
2020-11-27 09:45:11 +02:00
1c71815bd7
up_dac_channel: add register for dma data xbar
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This commit adds two fields:
1. source channel selection - Sets the channel number the for the source data.
2. DMA enable mask - When this bit is set do not drive the enable line
towards the DMA interface.
2020-11-27 09:45:11 +02:00
ad755788a0
ad9081_fmca_ebz/zc706: Initial version
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M=8 L=4 SampleRate=250 MSPS
LaneRate=10 Gbps
2020-11-12 15:46:27 +02:00
e9f319e3d7
ad9081_fmca_ebz: HP0 is already initialized in ZC706
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On carriers like ZC706 the HP0 interconnect is in already in use so it must
not be initialized here.
2020-11-12 15:46:27 +02:00
b080b52a14
daq3:zcu102: Connect overflow pins for the AD9680 TPL
2020-11-11 14:24:02 +02:00
2799777657
adrv9009zu11eg/adrv2crr_fmc: Fix hmc7044_car_gpio connections
2020-11-11 07:07:29 -05:00
ecd880d44c
adrv9009zu11eg:fmcomms8: Fix SPI timing constraint
2020-11-05 17:42:41 +02:00
7309da59d1
ad_ip_jesd204_tpl_dac: Switch to sync arm toggling instead of setting only
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Added the second flip flop for timing reasons
2020-11-05 17:42:41 +02:00
c3465789b8
up_dac_common: Move the sync status to register 0x1a to mirror adc path
2020-11-05 17:42:41 +02:00
685ca91f19
ad_fmclidar1_ebz/a10soc: Fix a typo
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Fixing a typo in projects/ad_fmclidar1_ebz/a10soc/system_top.v.
2020-11-05 12:53:50 +02:00
2ff5420630
Update system_top.v
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Add a comment that the spi CS decoding is tied to a setting in the device tree.
2020-11-02 16:59:08 +02:00
78b2ae02a1
ad9434_fmc,ad9467_fmc,fmcadc5: Update projects to use ad_iobuf, not IOBUF
2020-11-02 16:13:35 +02:00
a3a610728c
intel: Update projects to use ad_iobuf instead of ALT_IOBUF
2020-11-02 16:13:35 +02:00
ae7ec82334
adrv9009zu11eg: Update spi module to use generic verilog
2020-11-02 16:13:35 +02:00
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
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Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
912e09ad18
m2k: Add DAC last sample connections
2020-11-02 15:50:12 +02:00
0ddb08070a
axi_ad9963: Add last sample hold support
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The mechanism is controlled by axi_dac_interpolate.
2020-11-02 15:50:12 +02:00
4f4a4208cd
axi_dac_interpolate: Add last sample support
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This feature will allow the user to hold(indefinitely) the last sample, from an
ongoing DMA transfer, simple or cyclic(stooped by user or trigger).
This commit also adds as functionality option:
-synchronized stop between the two channels(DMAs)
-stop by trigger
2020-11-02 15:50:12 +02:00
d676cfd64f
adv7513/de10nano: Define the USB clock
2020-10-30 10:55:01 +02:00
c048a9243a
de10nano: Fix IO assignments
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- define IO assignments for HPS SPI master
- delete unused GPIO ports
2020-10-30 10:55:01 +02:00
04a694251e
axi_ad7616: Update ad_edge_detect port names
2020-10-28 11:31:50 +02:00
7cc5716ea8
ad469x: Remove sysid custom string init
2020-10-28 11:31:50 +02:00
5359d991b2
ad469x_zed: Update bd.tcl with new port names
2020-10-28 11:31:50 +02:00
d6f5c40e8b
ad_edge_detect: Change port names
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Fix critical warning for using reserved keyword as port name
2020-10-28 11:31:50 +02:00
ad4adddbe5
ad469x_fmc: Minor cosmetic update on the config file
2020-10-27 10:09:50 +02:00
0644edb389
fmcomms8: a10soc: Move RX and Observation to second SDRAM interface
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This is an attempt to get full bandwidth without a FIFO
2020-10-26 18:12:14 +02:00
3a5097875f
common: a10soc: Allow for the second SDRAM interface to be used at a different clock
2020-10-26 18:12:14 +02:00
6621fbec61
fmcomms8: a10soc: Initial commit
2020-10-26 18:12:14 +02:00
0413bea5c1
ad_ip_jesd204_tpl: Extend valid attribute ranges
2020-10-26 18:12:14 +02:00
35e4eb6a7b
ad469x: Add reference design for ad469x eval board
2020-10-22 19:17:10 +03:00
83cebe899f
daq3: Update projects to the new TPL
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Also modified the FIFO ports to have the same widths so that in a
future commit the bypass would be available for cases when the
sampling rate won't be the maximum rate or the number of channels
active will be less than maximum number of channels
2020-10-21 18:59:37 +03:00
9f58b465ea
adaq7980: Add AXI pulse generator to generate the offload trigger
2020-10-21 09:59:26 +03:00
7732a365b5
Revert "axi_spi_engine: Add pulse_width and pulse_period registers"
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This reverts commit 0402ce85e4164aa97ec3
2020-10-21 09:59:26 +03:00
37254358dd
makefile: Regenerate make files
2020-10-20 12:51:10 +03:00
b44df7a1e9
util_sigma_delta_spi: Fix syntax
2020-10-19 10:45:36 +03:00
1f6bba0aa1
ad77681: Add axi_clkgen ip for spi engine
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spi_clk changed from 40MHz to 80MHz
2020-10-19 10:42:21 +03:00
d6b23d5149
scripts/adi_pd_intel: Delete noisy print outs
2020-10-17 08:02:33 +03:00
66672932d5
adv7513/de10nano: Fix connection of ltc2308 SPI's interface
2020-10-14 10:37:14 +03:00
72635d73e3
cn0540: Add axi_clkgen to Makefile
2020-10-14 00:05:57 +03:00
f2f599ec60
axi_ad6676: Set data format to twos complement
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Set data format to twos complement to reflect the format defined in the
part data sheet.
2020-10-13 12:55:17 +03:00
c3983d779c
ad_ip_jesd204_tpl_adc: Fix PN check for twos complement data format
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For devices which have twos complement as data format the MSB of the raw
input must not be toggled.
2020-10-13 12:55:17 +03:00
6da4f61786
ad_ip_jesd204_tpl_dac_framer: fix localparam ordering
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The parameters were not in the order of invocation and this causes an
error in the vivado simulator (xsim).
2020-10-10 08:27:00 +03:00
9364c8501a
adrv9009_zu11eg: Add synchronization at application layer
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Switch RX path reset to be controlled by the TPL and use
RX SYSREF as external synchronization for the ADC TPL
Use TX SYSREF for synchornizing the TX DDS
2020-10-07 09:04:21 +03:00
4026eaa19b
ad9081_fmca_ebz: Fix device clocks termination
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The device clocks are AC coupled LVDS lines without external termination.
For proper operation internal differential termination must be enabled,
the DQS_BIAS will DC bias the AC coupled signal to VCCO/2 (1.8/2) 0.9V
2020-10-06 16:13:21 +03:00
1c208c01d6
ad9656:Add reference design for the ad9656 eval board ( #494 )
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Added reference design for the ad9656 evaluation board coupled with the
zcu102 carrier board. The JESD204 communication link that transfers data
from the 4 ADCs to the FPGA has the following paramenters : L=4, M=4, S=1,
F=2, HD=0, N=16, NP=16. The JESD204 line rate is configured to be 2.5GHz.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2020-10-06 09:53:40 +03:00
23cd6d2f91
sysid: Remove cstring init string
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These two projects were originally missed by the find/replace command
2020-10-02 23:34:40 +03:00
Laszlo Nagy
Adrian Costina
Istvan Csomortani
stefan.raus
aholtzma
IMoldovan
AndreiGrozav
sergiu arpadi
Josh Blum
hotoleanudan