By adding support for partial avalon transfers (data width < bus width),
valid data set size (DMA transfer length) will be dependent on the DMA bus
width only.
+ avl_write_transfer_done_s is a redundant net
+ specify the net state explicitly on if statements
+ to define the edge of avl_mem_fetch_wr_address signal,
its register and its second sync register should be used
The ad_mem_asym memory read interface has a 3 clock cycle delay, from the
moment of the address change until a valid data arrives on the bus;
because the dac_xfer_out is going to validate the outgoing samples (in conjunction
with the DAC VALID, which is free a running signal), this module will compensate
this delay, to prevent duplicated samples in the beginning of the
transaction.
+ all net names should have a *_s postfix
+ avl_burstcount is a constant 1, no need for an additional
register for it
+ all CDC should have two synchronization register, add
avl_last_beat_req_m2
The "'b0" constant will be translate as a 32 bit width vector by
ModelSim, and will throw a buswidth mismatch error. Tie the data_b
bus to zero, using its width parameter.
Currently the scripts use 'analog.com' as the vendor property for IP cores,
but 'ADI' for interfaces.
Make things consistent by using 'analog.com' for both interfaces as well
as IP cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Make sure that the XML files are re-build when any of the scripts that are
used to generated it are modified.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
All the rules to generate the XML files are the same. Reduce the number of
rules by useing wildcard matching for the rule target.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Convert the FMCOMMS11 project to the ADI JESD204 link layer cores. The
change is very straight forward, but a matching change on the software side
is required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Convert the FMCJESDADC1 project to the ADI JESD204 link layer core. The
change is very straight forward, but a matching change on the software side
is required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Convert the FMCADC4 project to the ADI JESD204 link layer core. The change
is very straight forward, but a matching change on the software side is
required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Convert the FMCADC2 project to the ADI JESD204 link layer core. The change
is very straight forward, but a matching change on the software side is
required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Convert the DAQ3 project to the ADI JESD204 link layer cores. The change is
very straight forward, but a matching change on the software side is
required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Convert the DAQ2 project to the ADI JESD204 link layer cores. The change is
very straight forward, but a matching change on the software side is
required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Convert the ADRV9371 project to the ADI JESD204 link layer cores. The
change is very straight forward, but a matching change on the software side
is required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Convert the AD6676EVB project to the ADI JESD204 link layer core. The
change is very straight forward, but a matching change on the software side
is required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Let the ad_xcvrcon handle the ADI JESD204 link layer cores. The function
will detect the JESD204 core vendor and connect the appropriate signals
based on it. This means it can still be used with the Xilinx JESD204 core
as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Istvan Csomortani
Rejeesh Kutty
Lars-Peter Clausen
Adrian Costina