1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
c1bdfca4c3
library: Delete all adi_ip_constraint process call
2017-04-06 12:36:47 +03:00
e0efbe210e
constraints: constraint files should be specified at adi_ip_files
2017-04-03 18:12:28 +03:00
d820d3d245
util_sync_constr: Preserve 1bit CDCs with ASYNC_REG true
2017-02-23 11:44:01 +02:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
9d1ae436b1
common/util_pulse_gen: Rename the ad_tdd_sync module
2016-06-09 10:07:47 +03:00
c293c04634
hdl make updates
2016-06-01 13:53:09 -04:00
e381d5170c
util_tdd_sync: Update the synchronization interface
...
Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-12 14:27:37 +02:00
bdf9754971
util_tdd_sync: Sync signals output reg is a false path source
2015-11-17 09:42:05 +02:00
a290611c09
util_tdd_sync: Initial commit
...
A synchronization signal generator for AD9361 running on TDD mode.
If the associated device is master, the module generates a pulse in a defined interval. Otherwise receives the sync signal from outside.
2015-11-11 10:46:11 +02:00
Istvan Csomortani
Adrian Costina
Rejeesh Kutty