4 Commits (0ffbe50163ac964d9c16708a626324d800274a92)

Author	SHA1	Message	Date
Istvan Csomortani	1c23cf4621	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
Istvan Csomortani	9d1ae436b1	common/util_pulse_gen: Rename the ad_tdd_sync module	2016-06-09 10:07:47 +03:00
Istvan Csomortani	e381d5170c	util_tdd_sync: Update the synchronization interface ... Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.	2016-02-12 14:27:37 +02:00
Istvan Csomortani	a290611c09	util_tdd_sync: Initial commit ... A synchronization signal generator for AD9361 running on TDD mode. If the associated device is master, the module generates a pulse in a defined interval. Otherwise receives the sync signal from outside.	2015-11-11 10:46:11 +02:00