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4 Commits (107b04355051afe8ee3006bd1ac2bfab7d40a05e)

Author SHA1 Message Date
Iulia Moldovan 28c06d505f Add/edit copyright and license for .v, .sv files 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-07-11 15:17:41 +03:00
Istvan Csomortani 157afcbc33 tb_base: Fix various test benches 
The tb_base.v verilog files does not contain a full module definition,
just some plain test code. In general the files is sourced inside the
test bench main module. As is, defining a timescale in these files will
generate an error, because timescale directive can not be inside a
module.

Delete all the timescale directive from these files.
 2019-05-17 11:20:48 +03:00
Adrian Costina 168e1951ee library: Add `timescale to modules that are missing it 2019-05-15 15:37:44 +03:00
Lars-Peter Clausen b3f027fc89 axi_dmac: Add simple register map testbench 
Add a testbench that exercises the basic functionality of the axi_dmac
register map module.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2018-05-03 14:49:06 +02:00