This commit removes two invalid ad_connect invocations, which weren't
caught in the original tests for commit cdda184007.
Signed-off-by: David Winter <david.winter@analog.com>
The goal of this commit is to make sure there isn't any significance to
the order in which parameters of ad_connect are specified.
As an example, previously you could only `ad_connect target VCC`, while
`ad_connect VCC target` would fail.
Note: This code intentionally ignores bd_{,intf_}ports, because
these can all be treated as bd_pins.
Signed-off-by: David Winter <david.winter@analog.com>
For fixing "Failed to reset the device and set SPI Config"
error, both clockPolarity and clockPhase should be disabled
or both enabled. By default both are unset.
Signed-off-by: Stefan Raus <stefan.raus@analog.com>
This commit fixes the 16.5Gbps lane rate case where the link drops
after few seconds an initial successful link up happens.
A few seconds delayed calibration process can workaround this but with
having the differential drivers swing increased this is no longer
required.
This will allow building base test harnesses and place on top of them
existing block designs for simulation purposes.
Test harnesses will contain basic functionality like
- clock and reset generators
- AXI master to aid register access of the cores.
- memory model of the DDR
- interrupt controller
Existing procedures (ad_mem_hp0_interconnect, ad_cpu_interconnect, ... ) will
connect to this harness as they do to a real base design.
To support deterministic latency with non-power of two octets per frame
(F=3,6) the interface width towards the transport layer must be resized
to match integer multiple of frames.
e.g Input datapath width = 4; Output datpath width = 6;
for F=3 one beat contains 2 frames
for F=6 one beat contains 1 frame
The width change is realized with a gearbox.
Due the interface width change the single clock domain core is split
in two clock domains.
- Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b
- lane rate / 20 for input datapath width of 8 octets 8b10b
- lane rate / 66 for input datapath width of 8 octets 64b66b
- Device clock : Link clock * input data path width / output datapath width
Interface to transport layer and SYSREF handling is moved to device clock domain.
The configuration interface reflects the dual clock domain.
If Input and Output datapath width matches, the gearbox is no longer
required, a single clock can be connected to both clocks.
David Winter
Laszlo Nagy
stefan.raus
sergiu arpadi
Owen McAree
vladimirnesterov