Rejeesh Kutty
|
c598e84258
|
remove processing order (no clock def dependency)
|
2017-02-22 16:02:08 -05:00 |
Adrian Costina
|
46290193f3
|
pzsdr2: ccusb, renamed clk_out to clkout_in
|
2017-02-14 11:58:11 +02:00 |
|
Adrian Costina
|
319a883c00
|
pzsdr2: Added FIFOs for DAC and ADC paths so that they work at l_clk/2 or l_clk/4
|
2017-01-18 12:00:10 +02:00 |
|
Adrian Costina
|
6e89ac3d65
|
pzsdr2: ccusb_lvds, add flag_a,flag_b signals
|
2016-11-30 17:39:02 +02:00 |
|
Adrian Costina
|
3d0049d274
|
pzsdr2: ccusb_lvdsr, updated project for the latest schematic
|
2016-11-22 16:55:52 +02:00 |
|
Rejeesh Kutty
|
cfd3ea61f1
|
pzsdr-to-pzsdr2
|
2016-11-14 14:12:22 -05:00 |