Commit Graph

159 Commits (118577f64fff08f3fee315a46e4852de99b6d818)

Author SHA1 Message Date
Istvan Csomortani 29a0f27cd1 ad_edge_detect: Add a flop to output, reset is active high 2015-12-14 15:40:29 +02:00
Istvan Csomortani d6eae81bc1 axi_ad7616: Add the control module to the core, finish up SPI integration 2015-11-13 18:14:21 +02:00
Rejeesh Kutty f1ed27105f library/common- reset fix 2015-10-23 14:32:35 -04:00
Istvan Csomortani 8ecdb4a4ca library/tdd_control: Add common registers to the register map and fix init value of a register
+ Software in general needs to have access to the VERSION register.
+ tdd_sync_d3 registers init value should be 1'b0
2015-10-16 11:57:54 +03:00
Adrian Costina 96d363849e ad_dds: Registered dds_scale so that Vivado can optimally map the dsp block 2015-10-09 13:43:14 +03:00
Rejeesh Kutty 5c3f90a676 up_gt: separate pll resets to tx/rx 2015-10-02 13:58:30 -04:00
Istvan Csomortani 97a9ecfc9a axi_hdmi_rx: Update constraint file and fix reset line 2015-09-29 18:49:30 +03:00
Istvan Csomortani b765be568f up_gt_channel: Delete the register, which stores transceiver type
Transceiver type is stored in axi_jesd_gt/up_gt only.
2015-09-29 14:23:42 +03:00
Istvan Csomortani cffb2e6226 up_gt_channel: Move the VERSION register to up_gt_channel, in order to preserve its address 2015-09-29 14:19:52 +03:00
Istvan Csomortani a0ac0e912b up/ad_gt_common/channel: Cosmetic changes 2015-09-29 14:16:24 +03:00
Istvan Csomortani c03983ca54 ad_tdd_sync/control: Update TDD logic
+ Redesign the TDD counter FSM
+ Make the sync logic independent from the tdd control
2015-09-25 19:11:23 +03:00
Adrian Costina 884f45c81d common library: Registered dc_filter and iq_correction coefficients 2015-09-16 14:24:18 +03:00
Istvan Csomortani 5bc16159fa ad_tdd_sync: The resync will reset all the control lines 2015-09-10 11:28:36 +03:00
Istvan Csomortani 85ffc25ec5 ad_tdd_sync: Update the synchronization logic
The synchronization interface is a single bidirectional line. Output for Master, input for Slave.
The sync_period value is relative to frame length and the digital interface clock. The actual synchronization
period will be: sync_period * frame_length * fb_clock_cycle
2015-09-09 12:31:58 +03:00
Istvan Csomortani 5a566b9e5d ad_tdd_control: Add delay compensation for the control lines 2015-09-09 12:24:26 +03:00
Rejeesh Kutty 1cd3435147 up_delay_cntrl- cosmetics 2015-08-28 13:16:18 -04:00
Rejeesh Kutty 8fddf983d2 up_hdmi_tx- common/generic instance names 2015-08-27 13:17:06 -04:00
Rejeesh Kutty 20ee10ea46 common/ad_lvds_out- add single ended 2015-08-27 11:41:47 -04:00
Rejeesh Kutty ba64de228e ip-constr- register name changes 2015-08-27 11:18:00 -04:00
Rejeesh Kutty 0077117f94 dac/adc- make common instances 2015-08-21 14:41:39 -04:00
Rejeesh Kutty c45d39df51 dac/adc- make common instances 2015-08-21 14:41:35 -04:00
Rejeesh Kutty e3ec6b48fc dac/adc- make common instances 2015-08-21 14:41:30 -04:00
Rejeesh Kutty f31c1c9caa dac/adc- make common instances 2015-08-21 14:41:26 -04:00
Rejeesh Kutty e4e4700950 dac/adc- make common instances 2015-08-21 14:41:13 -04:00
Rejeesh Kutty 54b4365f6c dac/adc- make common instances 2015-08-21 14:41:09 -04:00
Rejeesh Kutty 799001403f mult-macro: use primitive parameters 2015-08-20 13:54:16 -04:00
Rejeesh Kutty b0079e60bf ad-rst - common instance for adc/dac 2015-08-20 11:37:16 -04:00
Adrian Costina 6ae0c8f85e library: Fixed changes related to parameters 2015-08-20 18:13:54 +03:00
Rejeesh Kutty 928ee4972b dac/adc-rst: common ad-rst instance 2015-08-19 14:54:43 -04:00
Rejeesh Kutty 483e375910 dac/adc-rst: common ad-rst instance 2015-08-19 14:54:38 -04:00
Rejeesh Kutty f8b3346e97 axi_jesd_xcvr- ad_rst register changes 2015-08-19 13:26:38 -04:00
Istvan Csomortani 57cfb7cfb1 hdl/library: Update the IP parameters
The following IP parameters were renamed:

PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
Istvan Csomortani 10d9de39a1 axi_ad9361/tdd: Update the synchronization logic
The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 12:21:23 +03:00
Rejeesh Kutty 041be729f6 common/ip-constrs- uniform simple constraints will do 2015-08-13 13:03:51 -04:00
Rejeesh Kutty a2b816beda common/up_hdmi_tx: wrong clock on vdma status signals 2015-08-13 13:03:51 -04:00
Rejeesh Kutty 5edf61c40a ad_rst:- allow preset to be synchronized as reset 2015-08-13 13:03:51 -04:00
Rejeesh Kutty 2bcac36e33 common/up_- change to asynchronous resets 2015-08-13 13:03:51 -04:00
Rejeesh Kutty 10d4da64dd axi_jesd_gt: move master/slave control to a util module 2015-08-13 13:03:51 -04:00
Rejeesh Kutty e4f94664a6 axi_jesd_gt- remove per lane control/status to channel 2015-08-13 13:03:51 -04:00
Rejeesh Kutty f807490ed1 axi_jesd_gt- per lane group 2015-08-13 13:03:51 -04:00
Rejeesh Kutty 4c8206608c axi_jesd_gt- separate es-axi 2015-08-13 13:03:51 -04:00
Rejeesh Kutty e4b0710923 axi_jesd_gt- per lane split-up 2015-08-13 13:03:51 -04:00
Istvan Csomortani ad80561379 TDD_regmap: Fix CDC for control signals 2015-08-06 15:16:39 +03:00
Istvan Csomortani e19d476b58 TDD_regmap: Fix addresses 2015-08-06 15:15:50 +03:00
Istvan Csomortani d2c99acae8 fmcomms2/TDD: Update synchronization interface
Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
Istvan Csomortani 8e631e56d6 fmcomms2: Add a synchronization interface for TDD mode.
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write  0x01 into TDD register 0x50.
2015-07-28 14:42:54 +03:00
Rejeesh Kutty cd5ce3349f iqcor- move i/q sel inside the module 2015-07-23 15:55:45 -04:00
Rejeesh Kutty a4461545fa axi-ip: constraints - altera 2015-07-22 12:46:06 -04:00
Rejeesh Kutty 559893c0a3 altera- obsolete cores 2015-07-21 11:04:26 -04:00
Rejeesh Kutty 86dabbe5fc jesd-align-- xilinx/altera merge 2015-07-21 10:57:00 -04:00