When having multiple DMA cores sharing the same constraint file Vivado
seems to apply the constraints from the first core to all the other cores
when re-running synthesis and implementation from within the Vivado GUI.
This causes wrong timing constraints if the DMA cores have different
configurations. To avoid this issue use a TTCL template that generates a
custom constraint file for each DMA core instance.
This also allows us to drop the asynchronous clock detection hack from the
constraint file and move it to the template and only generate the CDC
constraints if the clock domains are asynchronous.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.
The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
Move the axi_repack block to its own module. This allows it to use it
outside of the DMA controller.
Also rename it to util_axis_resize to better reflect its function.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Adrian Costina
Rejeesh Kutty
Istvan Csomortani
Lars-Peter Clausen