0b58a2a1db
avl_adxcvr- sysclk frequency
2016-11-09 09:21:07 -05:00
48ee720901
avl_adxcvr- a5 requires single transceiver controller
2016-11-08 15:20:01 -05:00
a58597c13a
ad9250 - build fixes
2016-11-08 15:17:54 -05:00
d7357d781b
axi_ad9250 - avalon/axi streaming + sof
2016-11-04 15:30:39 -04:00
ee9c8b884d
avlxcvr- add arria v support
2016-11-04 15:01:19 -04:00
9dc7f16d80
axi_usb_fx3: Added zero length packet capability
2016-11-03 15:29:56 +02:00
1e0fed82f7
alt_serdes- a10 ddio fixes
2016-11-01 12:41:25 -04:00
5eff357568
up_tdd_cntrl: Fix memory map register writes
2016-11-01 10:06:57 +02:00
9f4c5f8060
arradio/ad9361- updates
2016-10-31 15:34:32 -04:00
b94cc8afb1
altera- cmos cores
2016-10-31 13:13:48 -04:00
e0459df0f3
altera -c5 qsys alternative
2016-10-31 11:18:27 -04:00
cc75fa3dfe
altera- java/tcl mess handling
2016-10-31 10:54:07 -04:00
a9d03af771
altera- serdes changes
2016-10-28 14:09:18 -04:00
f2e12cc88f
util_fir_dec: Shifted the output data to the left so that the amplitude remains
...
constant
2016-10-28 15:18:36 +03:00
d9b756e7ad
util_fir_int: Shifted the output data to the left so that the amplitude remains constant
2016-10-28 15:17:30 +03:00
30314e4492
library: Added util_fir_int and util_fir_dec interpolation/decimation filters
2016-10-27 19:31:50 +03:00
8107514dde
altera/common- ad_serdes_clk
2016-10-27 09:41:10 -04:00
f7e3703b98
axi_ad9371- avalon-s interfaces
2016-10-27 09:25:00 -04:00
6f611e0d10
altera/alt_serdes: Add support for Cyclone V
2016-10-25 20:32:51 +03:00
08cef5a745
axi_ad9361: Add Cyclone V SERDES support
2016-10-25 20:24:17 +03:00
5731ba3300
fmcomms11- xcvr updates
2016-10-24 09:51:40 -04:00
de0c487195
axi_ad9684: Add Altera support for the core
2016-10-24 11:43:22 +03:00
3f3606d318
axi_ad9122: Add Altera support for the core
2016-10-24 11:43:12 +03:00
aa46de5e5e
adi_ip_alt: Add ad_generate_module_inst proc
...
Add a tcl process, which can be used to generate custom module
names during the generation phase. This will be used to create
different ad_serdes_clk module, in case when independent IOPLLs are
needed for TX and RX.
2016-10-24 11:43:00 +03:00
707038937a
alt_serdes: Add additional parameters
...
Add additional parameters to keep the top of ad_serdes_* modules
consistant through differente carriers.
2016-10-24 11:42:43 +03:00
8dbfe9258f
axi_ad9162: Delete duplicated port
2016-10-21 13:47:01 +03:00
0beecea02d
util_adxcvr- ultrascale updates
2016-10-19 13:06:10 -04:00
72c05e8635
axi_dmac: Fix constraints for ultrascale
...
Replace "PRIMITIVE_SUBGROUP == flop" with "IS_SEQUENTIAL" as the former is
series7 specific while the later works on all platforms. This fixes the
axi_dmac timing constraints for ultrascale based platforms.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-10-19 14:00:54 +02:00
ecc0addb8c
scripts/adi_ip_alt.tcl: Script is case insensitive for its arguments
2016-10-18 11:25:06 +03:00
bf949f1a88
axi_xcvrlb- xcvr updates
2016-10-17 16:16:57 -04:00
1b3fcb5863
util_adxcvr- parameter defaults
2016-10-17 16:10:57 -04:00
a026d44435
axi_generic_adc: Add missing up_adc_common connections
2016-10-12 13:20:26 +03:00
b543402051
axi_mc_current_monitor: Add missing up_axi connection
2016-10-12 13:20:26 +03:00
91995c082d
axi_ad9684: Fixed up_drp_*data width
2016-10-12 13:20:26 +03:00
a505d304af
Add up_dac_common missing connections
2016-10-12 13:20:26 +03:00
43ee917d53
Add up_dac_channel missing connections
2016-10-12 13:20:26 +03:00
1131be91ed
axi_ad9361: Makefile update
2016-10-11 23:34:13 +03:00
b7767aa18f
xilinx/axi_ad9361_lvds_if: Remove ila
2016-10-11 18:13:45 +03:00
2d93d787ab
altera/ad_cdfilter: Update interface to Verilog 2001 standard
2016-10-11 17:59:21 +03:00
369dad60b0
axi_ad9361: Add Altera SERDES interface support
2016-10-11 17:59:19 +03:00
ae47895666
altera/alt_serdes: Fixed SERDES 4 factor initialization
2016-10-11 17:59:17 +03:00
d41945f568
altera/ad_serdes: Add support for any SERDES factor less than 8
2016-10-11 17:59:14 +03:00
52194f0fea
axi_ad9361: Add DRP connection to the interface module
2016-10-11 17:59:12 +03:00
7194d2eccc
axi_ad9361: Grup interfaces to add support for more carriers
2016-10-11 17:58:49 +03:00
cc6ca4f0f2
ad_lvds_in- ultrascale sim device
2016-10-10 10:39:47 -04:00
121b341b45
axi_spdif_rx: Fixed version register issue. Added sampled_data to sensitivity list
2016-10-10 17:30:13 +03:00
ff980551e6
ad_serdes: SERDES_FACTOR handover missing
...
In modules ad_serdes_in/ad_serdes_out the handover of the parameter
SERDES_FACTOR did not exist, causing unwanted behavioral in case of
factors less than 8.
SERDES_FACTOR must be hand over to DATA_WIDTH parameter of the SERDES
primitive.
2016-10-10 16:38:42 +03:00
f34aa67029
axi_hdmi: Fix a typo
2016-10-10 16:22:18 +03:00
15f36af4c2
axi_ad9152: Update core to support Altera platforms
2016-10-10 16:21:49 +03:00
111adac825
axi_usb_fx3: Updated core
...
- trig signal will reset state machine
- slrd_n delay will be absorbed by the axi_usb_fx3_if module, when Xilinx DMA is not ready to receive data during a packet
- fx32dma_eop signals when the FX3 DMA buffer should be empty. slrd_n set high and sloe_n set low for another two clock cycles
- eot_fx32dma signals the interface that the packet has been fully transfered. No need for watermark signals
- added length_fx32dma and length_dma2fx3 as requested
2016-10-10 10:33:37 +03:00
39fdf11ef3
util_adxcvr- rx/tx clocks
2016-10-05 13:53:02 -04:00
7ec93ce8e0
util_adxcvr: Fix some typo
...
GTHE4_CHANNEL is instantiated in case of XCVR_TYPE == 2
2016-10-05 17:42:12 +03:00
4f587d2e48
util_adxcvr: Delete trailing whitespaces
2016-10-05 17:41:40 +03:00
1b9d2d434c
axi_ad9361_tdd: Delete unused register
2016-10-05 17:41:08 +03:00
ddceff2b5c
axi_usb_fx3: Updated header/footer signature
2016-10-04 16:11:24 +03:00
48dd4880a3
util_adxcvr- ultrascale+ initial commit
2016-10-03 16:11:45 -04:00
0e8551545c
util_adxcvr- ultrascale+ initial commit
2016-10-03 16:11:45 -04:00
b4652650e4
util_adxcvr- xcvr_type parameter
2016-10-03 16:11:45 -04:00
63ddcf1e26
util_adxcvr- synthesis warnings fix
2016-10-03 16:11:45 -04:00
8e0dc859af
axi_usb_fx3: Update
...
- added 1 clock delay for slrd_n signal
- rearrange databytes
2016-10-03 15:17:01 +03:00
43b3761b80
axi_ad9361: Flop the tx and rx valid
2016-10-03 12:24:04 +03:00
8e25bc01b3
all: Change tab to double space
...
Occasional file parsing and restructuring become a pain, if tabs exists
in code. General rule of the repos is tab always a double space.
2016-10-01 18:13:42 +03:00
6b956066ef
xilinx/ad_lvds*- ultrascale+
2016-09-30 11:55:10 -04:00
e9105faae1
library/scripts- add beta devices
2016-09-30 11:55:10 -04:00
c072c2f89a
util_clkdiv: Add IP
2016-09-30 17:13:51 +03:00
7290bcc81a
hdlmake- updates
2016-09-29 11:50:58 -04:00
ffec95f220
ad9371- xcvr updates
2016-09-29 11:50:58 -04:00
b4fac96aad
axi_ad9361- independent disables
2016-09-28 15:45:27 -04:00
f7fb3ccaca
axi_ad9361: Change the data path gating
...
Bring up the datapath gating from the TDD controller module.
2016-09-28 16:36:13 +03:00
df485d7878
axi_ad9684: Fix the PN9 PRBS sequence monitor
2016-09-28 10:47:16 +03:00
9defccef70
dacfifo- axi address map fixes
2016-09-27 14:48:23 -04:00
c98e2e95dd
ad9162- xcvr updates
2016-09-26 15:21:45 -04:00
692cb10fb2
ad9625- xcvr updates
2016-09-26 15:21:11 -04:00
ad16aec101
axi_ad9684: Fix SERDES modules
2016-09-26 11:14:35 +03:00
f6c7aa9005
library- dac parameter changes
2016-09-23 16:15:59 -04:00
1a11e28821
ad9361- dac data path split
2016-09-23 16:13:46 -04:00
6735333aea
common- dac data path split
2016-09-23 16:13:24 -04:00
6837143110
library/ adc parameter changes
2016-09-23 13:44:47 -04:00
7be6168b2e
ad9361- adc data path split
2016-09-23 13:42:14 -04:00
8729af1b91
common- adc- data path disable split
2016-09-23 13:40:35 -04:00
78f7384150
ad9361- vivado synthesis warnings fix
2016-09-22 13:41:18 -04:00
2b6eb1d65e
up_drp: Revert some bit locations
...
Linuxe drivers are checking the drp_locked status even if the
core does not contains a clock generation/managment module. To
not break all the designs, revert all the status and control bits to
there old locations.
2016-09-22 16:32:42 +03:00
21b5e9c634
hdlmake- updates
2016-09-21 11:56:03 -04:00
0def596b43
axi_xcvrlb- updates
2016-09-21 11:04:22 -04:00
d497a7b0ae
axi_xcvrlb- constraints
2016-09-21 11:04:22 -04:00
a21b9fe8ff
up_drp: Fix up_drp_wr
2016-09-21 17:55:58 +03:00
64cd7dc002
axi_ad9122: Update core to the new DRP interface
2016-09-21 16:09:55 +03:00
bae839acd4
axi_ad9739a: Update core to the new DRP interface
2016-09-21 15:23:08 +03:00
781702c1b9
axi_ad9434: Update the core to the new DRP interface
2016-09-21 15:12:59 +03:00
913eafed48
up_drp : Update the DRP interface to support Altera platforms
2016-09-21 15:00:45 +03:00
10408b8c88
up_tdd_cntrl: Set PCORE version to 1.00.a
2016-09-21 10:27:28 +03:00
1860d72df6
axi_xcvrlb- updates
2016-09-19 12:39:59 -04:00
5592c2780e
axi_xcvrlb- loopback version
2016-09-19 12:39:59 -04:00
38f1521861
xilinx/ad_serdes_in : Fix some typos
2016-09-19 16:02:52 +03:00
ff0f659a33
xilinx/ad_serdes_clk : Rename parameter MMCM_DEVICE_TYPE to DEVICE_TYPE
2016-09-19 16:02:06 +03:00
2159f78c80
axi_ad9361: Delete invalid assignment of a generated wire
2016-09-16 17:38:08 +03:00
6510f92c12
ad_serdes : Cosmetic changes
2016-09-16 14:45:39 +03:00
13a35f7a2a
altera/ad_serdes_clk: The IO_PLL reset is active heigh
2016-09-16 14:20:39 +03:00
858ea09048
altera/ad_serdes_in: Fix some typos
2016-09-16 10:56:16 +03:00
a2d15acb89
ad_serdes- altera/xilinx sync
2016-09-15 13:33:55 -04:00
63696c1a28
alt_serdes- data-width parameter
2016-09-15 11:12:18 -04:00
02dfd2d2e2
altera/ad_serdes_out- sample transmit order
2016-09-15 10:28:34 -04:00
5986f45cba
altera/ad_serdes_out- updates
2016-09-15 09:38:11 -04:00
16ee1336c3
Makefile: Update make files
2016-09-15 11:41:06 +03:00
3b0c1e02fc
axi_dacfifo: Move IP to library/xilinx
2016-09-15 11:38:16 +03:00
3cbbc771a8
axi_adcfifo: Move IP to library/xilinx
2016-09-15 11:36:47 +03:00
fe133a7c39
v2001- parameter defines
2016-09-14 15:47:45 -04:00
16046a984c
alt_serdes- updates
2016-09-14 12:05:48 -04:00
4a6b554c0a
ad_serdes- updates
2016-09-14 11:12:53 -04:00
343056b674
axi_usb_fx3: Update IP to work with 2016.2
2016-09-14 15:40:42 +03:00
a0318ae868
ad_serdes_clk- syntax errors
2016-09-13 14:02:11 -04:00
734b39a8ed
alt_serdes: Fix some issues in the _hw.tcl script
2016-09-13 17:42:51 +03:00
bced17a16f
axi_ad9144- qsys updates
2016-09-12 14:57:50 -04:00
01b7662e05
axi_ad9680- qsys updates
2016-09-12 14:57:50 -04:00
c6998dd396
scripts- altera conduit
2016-09-12 14:57:50 -04:00
73ebf1225c
axi_adxcvr- ip/phy split
2016-09-12 14:57:50 -04:00
21545ee83f
avl_adxcvr- ip/phy split
2016-09-12 14:57:50 -04:00
8718b7f477
avl_adxphy- ip/phy split
2016-09-12 14:57:50 -04:00
d30ffdb7e9
avl_adxcfg- ip/phy split
2016-09-12 14:57:50 -04:00
9159e31244
axi_adxcvr- compile fixes
2016-09-12 14:57:50 -04:00
5a309d8863
avl_adxphy- split
2016-09-12 14:57:50 -04:00
2a34f9baa8
alt-serdes, in & out
2016-09-12 11:45:23 -04:00
9e0c39a71b
alt_serdes_clk- changes
2016-09-12 10:30:28 -04:00
f4be0524b4
altera/common: Add SERDES related modules
2016-09-09 18:04:41 +03:00
a183e51a12
axi_ad9361: Add parameter R1_MODE_EN
...
R1_MODE_EN can disable the second I/Q channel of the core. This way
the user can save resources by cutting down the size of the core.
2016-09-09 16:34:11 +03:00
e42206e510
axi_ad9361: Add a TDD enable/disable parameter
2016-09-09 14:38:28 +03:00
be41a8bcaa
axi_ad9361: Delete debug ports of the tdd module
2016-09-09 14:38:28 +03:00
bbcf2a3ec3
axi_ad9434/axi_ad9434_constr: Change constraint file to resolve critical warning
2016-09-01 17:16:59 +03:00
4ae084ee32
avl_adxcvr- compile fixes
2016-09-01 10:06:28 -04:00
5544e3cf10
axi_adxcvr- compile fixes
2016-09-01 10:06:28 -04:00
230f1526c0
avl_adxcfg- compile fixes
2016-09-01 10:06:28 -04:00
b7ea2efa87
altera- xcvr cores
2016-08-29 15:18:48 -04:00
9799599eee
library/ad9361- add dac clk sel
2016-08-26 10:31:00 -04:00
74bc498a6d
library/common- added dac clock select
2016-08-26 10:31:00 -04:00
10b9a0e52f
upadated xcvr ips
2016-08-17 15:51:55 -04:00
6a8ca8107a
common: Added common ad_dcfilter stub for altera.
2016-08-16 17:37:16 +03:00
e754f0a46a
up_axi- writes dropped by delayed w-responses
2016-08-14 11:21:19 -04:00
3427965cd2
adxcvr- add u-gth bufg
2016-08-11 10:00:41 -04:00
bb9cb86f34
adc/dac- fifo constraints
2016-08-11 10:00:41 -04:00
829e4155ca
modified transceiver configuration files
2016-08-10 14:59:38 -04:00
b8f4e1c0aa
updated 9680 hdl files(to resolve a critical warning)
2016-08-10 14:50:31 -04:00
ccf1c56b33
util_upack: Patch up the description of Altera IP
2016-08-08 16:39:56 +03:00
e9ac4a5a0e
util_rfifo: Patch up the description of Altera IP
2016-08-08 16:39:25 +03:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
aad8c265bc
lib_refactoring: Fix path for CMOS sources
2016-08-08 15:07:54 +03:00
1d33d7d7ee
lib_refactoring: Move the CMOS interface modules to ~/library/xilinx/common
2016-08-08 15:07:42 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
90ac7b7ac9
lib_refactoring: Move all Altera module to library/altera/common
...
Move all Altera modules to library/altera/common, delete the
deprecated wrapper files
2016-08-08 15:07:01 +03:00
cb9af99c5d
lib_refactoring: Add ad_mul.v for Altera
2016-08-08 15:06:48 +03:00
b806fa3b42
lib_refactoring: Move all the Xilinx common modules to library/xilinx/common
2016-08-08 15:06:10 +03:00
5faf4c4976
cleanup: Don't need Makefiles specific to xilinx/altera libraries. Top Makefile covers them
2016-08-05 16:27:52 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
cb23ba8bb7
make- script needs update
2016-08-04 14:17:04 -04:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
2b7c976be5
xcvr- altera/xilinx split
2016-08-04 13:26:10 -04:00
cba53774ca
axi_dmac: Don't add CDC constraints when all clocks are synchronous
...
When all clocks are synchronous there are no synchronizers and the
constraint for the CDC registers can't find any cells which generates a
warning. To avoid this don't add CDC constraints when all the clocks are
synchronous.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-02 19:30:24 +02:00
aece3f5555
axi_ad9680: Update IP core
...
- added signals so that AD9680 can be connected to altera's xcvr core through an avalon streaming sink
- added DEVICE_TYPE parameter in _hw.tcl, set to 1 for altera
2016-08-01 15:05:30 +03:00
a0ae791395
hdl-vivado-2016.2: Update axi_jesd_gt
...
Infer AXI bus interfaces separately.
2016-08-01 13:53:18 +03:00
fbe3d75eb0
cosmetics: Delete trailing whitespace characters
2016-08-01 13:46:46 +03:00
b99117e686
up_axi: Same cycle BVALID/READY fails on Altera
...
The Qsys interconnect does not handle the assertion of BVALID on the
same cycle as [A]WREADY. Add a single cycle of delay to prevent
deadlocks.
Similar to:
2817ccdb22
2016-08-01 12:17:10 +03:00
58b220ba81
ad_tdd_control: Add an on/off switch to the receive datapath
...
For a more robust control, add an on/off switch to the receive datapath too,
in order to filter out transition noises.
2016-08-01 11:49:27 +03:00
7988d2c7a2
adi_ip: remove duplicated errored auto address maps & interfaces
2016-07-29 12:32:19 -04:00
4aa506de8d
adxcvr- added a space?
2016-07-29 09:38:08 -04:00
71dad14e0e
axi_adcfifo- disable auto infer mess-up
2016-07-29 09:37:17 -04:00
39ff059ef6
hdl-vivado-2016.2- productivity decimated again!
2016-07-28 13:44:57 -04:00
d5d61ff518
hdl-vivado-2016.2- productivity decimated again!
2016-07-28 13:44:57 -04:00
52b544bb66
hdl-vivado-2016.2- auto infer bus interfaces
2016-07-28 13:44:57 -04:00
3384d384d3
hdl-vivado-2016.2- infer bus interfaces separately
2016-07-28 13:44:57 -04:00
c316f0dfea
ad9144- synthesis warnings fix
2016-07-28 13:44:57 -04:00
8a2734b43e
up_dac_common- typo- unf register reset
2016-07-28 13:44:57 -04:00
6ebb32a194
library axi-slave missing protection signal added
2016-07-22 12:54:27 -04:00
39a5534e00
hdlmake- updates
2016-07-21 16:10:38 -04:00
5c91e41da8
ad9680- sof + sample delineation
2016-07-21 16:09:33 -04:00
db6d5f509f
library/common- xcvr interface logic
2016-07-21 16:09:33 -04:00
75864f0ce5
util_adxcvr- add constraints file
2016-07-21 16:09:33 -04:00
1435c5f7f7
util_adxcvr- add clock buffers, rst-done, rate on usrclk
2016-07-21 16:09:33 -04:00
8e04e70791
axi_adxcvr- status output for jesd ip
2016-07-21 16:09:33 -04:00
1f25d7f637
axi_adxcvr- self-disable based on num of lanes
2016-07-21 16:09:33 -04:00
c797a579f1
util_adxcvr- rstdone on usrclk2
2016-07-21 16:09:33 -04:00
ced36f6159
up-dac- support iq mode
2016-07-21 11:58:03 -04:00
3a1ecb7463
ad9162- support iq mode
2016-07-21 11:58:03 -04:00
040f72d172
ad_mul_u16: Delete unused module
2016-07-20 14:17:04 +03:00
2dd6bb0cb8
up_drp_cntrl: Delete unused module
2016-07-20 14:17:04 +03:00
af9915b060
up_axis_dma_*: Delete unused modules
2016-07-20 14:17:04 +03:00
df43ca9332
ad_axis_dma_*: Delete unused modules
2016-07-20 14:17:04 +03:00
46b00aea2d
util_adc_pack: Delete unused IP core
2016-07-20 14:17:04 +03:00
8902a31ca6
util_dac_unpack: Delete unused IP core
2016-07-20 14:17:04 +03:00
634924246a
axi_jesd_xcvr: Delete Makefile
...
This core is an Altera core only, no need for Makefile.
2016-07-20 14:17:04 +03:00
74c220d79e
make: Update Make files
2016-07-20 14:17:04 +03:00
b9a5bb3549
axi_dacfifo: Optimize the AXI read logic
...
Save the valid AXI beats number of the last AXI transaction, and the valid
DMA beats number of the last AXI beat, so the read back logic can use this
data and prevent to feel up the CDC memory with invalid samples. Also in
this way the end of the read back cycle get a more robust control: no more
duplicated samples at the end of the buffer.
2016-07-20 11:49:06 +03:00
e46990e508
axi_dacfifo: Cosmetic changes
...
Rename a few registers and fix indentation.
2016-07-20 11:49:06 +03:00
b48401175a
axi_dacfifo: Optimize the AXI write logic
2016-07-20 11:49:06 +03:00
74f45cff24
axi-ad9625: fix clock ratio to match sampling clock
2016-07-19 16:21:13 -04:00
1df942b752
rfifo- buffer 1 seg before read
2016-07-12 10:24:22 -04:00
4f0d7bd6eb
util_wfifo: read after write is complete
2016-07-11 09:59:31 -04:00
832efdc99c
hdlmake updates
2016-07-08 13:58:56 -04:00
7a03d44e4e
adxcvr- clock buffers are removed
2016-07-08 13:57:27 -04:00
20ac95b1ec
adxcvr- initial commit
2016-07-08 13:57:27 -04:00
48762519b5
make updates
2016-07-06 15:02:00 -04:00
427cc84bb2
axi_ad7616: Rename the physical interface signals to rx_*
...
No functional modification.
2016-07-01 14:45:23 +03:00
d931b2ee64
ad9162 core verilog files
2016-06-30 10:24:01 -04:00
8d558b2538
make: Update Make files
2016-06-29 14:50:07 +03:00
18e28b01fd
axi_ad7616: Add burst counter to the parallel interface
...
With this counter the parallel logic supports the burst sequencer.
2016-06-29 14:17:28 +03:00
e6494b9a74
axi_ad7616: Change the DMA interface type to Write FIFO
2016-06-29 14:11:02 +03:00
64633e519c
Merge remote-tracking branch 'origin/dev_ad7616' into dev
2016-06-29 12:32:39 +03:00
cdf01a492e
library/axi_dacfifo: Update the bypass logic
...
The bypass logic is located between the AXI read controller and the
DAC CDC fifo. When the bypass is enabled the DMAC destination interface
must be clocked with the PL_DDR controller's ui_clk. This way it can easily
switch between the AXI read's stream and DMAC's stream interface.
2016-06-22 12:24:54 +03:00
def47dd536
interfaces: added xcvr interfaces
2016-06-17 12:00:15 -04:00
36fbf4fc42
util_adxcvr: shared xcvr cores
2016-06-17 11:59:42 -04:00
87cf13b0ef
util_adxcvr- system verilog interfaces
2016-06-16 16:41:43 -04:00
80ce7aeb66
util_adxcvr- updates
2016-06-16 16:40:57 -04:00
7c762f63a8
library/axi_dacfifo: Fix the control logic of the write side
...
Fix the control logic for the AXI write transactions.
2016-06-15 13:49:00 +03:00
d5ce137c55
library/axi_dacfifo: Fix reset for a few registers
2016-06-15 13:49:00 +03:00
10090a296e
library/axi_dacfifo: Cosmetic changes
...
Rename a few registers and improve consistency.
2016-06-15 13:49:00 +03:00
7485d27d37
ad9361/altera- device-family variable
2016-06-14 12:28:13 -04:00
5d437083cc
ad9361/altera- a10+ only
2016-06-14 12:19:54 -04:00
dc45287b14
util_adxcvr- added
2016-06-14 12:19:18 -04:00
c19ed4c8ef
axi_hdmi_tx_core: Fixed embedded sync synchronization signals
2016-06-14 14:30:28 +03:00
aee38e1cc9
up_hdmi_tx: Fixed data path width
2016-06-14 14:27:03 +03:00
27fd5f5bdc
modified prbs7 and prbs15 gereration code
2016-06-13 14:44:03 -04:00
83dd7e91c4
deleted pn23 and pn 31, data width yet to be modified
2016-06-13 14:44:03 -04:00
341b7badee
library/scripts: Remove all autogenerated interface in adi_ip_properties_lite
...
There are a few IP, which is configured by using just the adi_ip_properties_lite
process, therefor the remove_all_bus_interface will be called in the end of that
process, to make sure that all the autogenerated interfaces are deleted during the
IP properties setup.
2016-06-10 15:08:05 +03:00
9d1ae436b1
common/util_pulse_gen: Rename the ad_tdd_sync module
2016-06-09 10:07:47 +03:00
abe837e608
util_rfifo: Set an offset for the write addres
2016-06-02 17:34:29 +03:00
c293c04634
hdl make updates
2016-06-01 13:53:09 -04:00
3832f2669e
axi_jesd_xcvr: support tx/rx disable
2016-06-01 13:48:51 -04:00
54f398cc36
ad9371-hw- add dsp slice
2016-06-01 13:48:51 -04:00
e1495b89f9
axi_dacfifo: Cosmetic changes
2016-05-27 14:13:55 +03:00
c724c027c4
axi_dacfifo: Fix the synchronizers
2016-05-27 14:13:55 +03:00
183c67aca0
axi_dacfifo: Update the axi write controller
...
Do some refactoring and add a DMA beat counter.
2016-05-27 14:13:55 +03:00
8caa783f5c
axi_dacfifo: Update the constraints
2016-05-27 14:13:55 +03:00
3b6a36e3e2
axi_dacfifo: Increase the ASYM_MEM depth in the DAC side
...
Increase the asymetric memory depth on the DAC side. Increase the
data width of the grey coder and decoder.
The controller fills up the CDC memory with three AXI burst, to prevent
underflow on the wrap arounds.
2016-05-27 14:13:55 +03:00
c8d4f956e7
axi_dacfifo: Update the read back logic
...
Update the readback logic of the FIFO. The controller uses a
relative address counter, which counts the DMA beats. The readback
logic uses the last value of that counter to define the wrapping
address. The aditional data from the last AXI burst, if there is any,
will be dropped.
2016-05-27 14:13:55 +03:00
88e0cfec42
axi_dacfifo: The AXI read and write have the same properties
...
AXI read and AXI write channel have the same SIZE and LENGTH.
2016-05-27 14:13:55 +03:00
aca3038919
axi_dacfifo: No overflow for DAC
2016-05-27 14:13:55 +03:00
81ade7f26c
axi_dacfifo: Fix resets
...
DMA side: axi_resetn is used to reset the address counters
DAC side: GT tx_rst is used to reset the last_address register
2016-05-27 14:13:55 +03:00
578376c8fe
axi_dacfifo: Add bypass logic
2016-05-27 14:13:55 +03:00
f10c1e6e93
axi_hdmi_tx: Remove hdmi_full_range register
2016-05-27 14:04:40 +03:00
05ac271aff
daq3/a10gx- qsys modifications
2016-05-24 03:15:24 -04:00
d254fa841b
library- altera updates
2016-05-23 10:55:07 -04:00
3f00614bc7
axi_jesd_xcvr: rx/tx only select
2016-05-20 16:13:36 -04:00
f1a603a3b1
ad9371- altera ip
2016-05-20 15:16:36 -04:00
09520709b0
make updates
2016-05-20 12:35:45 -04:00
b5b05bb9d1
axi_ad9371: added
2016-05-20 11:41:54 -04:00
bf0b90229a
rfifo/wfifo- qsys ip
2016-05-18 13:24:13 -04:00
7fdaee186c
upack/cpack- qsys ip
2016-05-18 13:24:13 -04:00
a262eb7ab3
ad9361- output-rst - associated-rst issue?
2016-05-18 13:24:13 -04:00
e15893444c
upack- fix interface names
2016-05-18 13:24:13 -04:00
285cbc7225
xfifo- fix sdc/xdc names
2016-05-18 13:24:13 -04:00
d7f0bd1b76
ad9361- add reset sink
2016-05-18 13:24:13 -04:00
bb4ed42a93
ad9361- add missing wires
2016-05-18 13:24:13 -04:00
42b0fabd40
axi_hdmi_tx_core: Fixed data path
2016-05-17 14:41:18 +03:00
68329de738
ad9361- interface updates
2016-05-16 12:19:38 -04:00
421c0519f4
util_rfifo- updates
2016-05-16 12:19:38 -04:00
e05204a86d
util_cpack: interface updates
2016-05-16 12:19:38 -04:00
6bc05fc844
ad_*_in: register post-iob
2016-05-16 12:19:38 -04:00
cd7c9c99ed
ad_*_clk: altera-pll not supported by qsys flow
2016-05-16 12:19:38 -04:00
4fbff45e27
util_wfifo- updates
2016-05-16 12:19:38 -04:00
f515885fc4
util_wfifo: altera ip
2016-05-16 12:19:38 -04:00
58a2a3259c
util_rfifo: updates
2016-05-16 12:19:38 -04:00
82d43783f1
util_rfifo: altera ip
2016-05-16 12:19:38 -04:00
31671bf9d5
util_rfifo: constraints
2016-05-16 12:19:38 -04:00
aadb220a3f
zcu102- updates
2016-05-10 15:40:41 -04:00
3871d3ce2b
ad9361-c5/a10 - updates
2016-05-09 13:54:08 -04:00
9cd6e2da51
quartus-mess- altddio direct instantiation
2016-05-09 13:54:08 -04:00
726ddb6e93
ad_lvds_clk: Fixed assignment mismatched
2016-05-09 10:32:18 +03:00
b0538a03a2
Make: Update
2016-05-06 16:44:24 +03:00
b36c722ec9
up_hdmi_tx: Discard the standard default values
...
Restore the base functionality of the core. Changing the data format
will not set by default its standard maximum and minimum data clipping
ranges.
2016-05-05 13:41:46 +03:00
68d83def01
axi_hdmi_tx_core: Fixed data path
2016-05-05 13:32:25 +03:00
0d2dc2c62b
axi_hdmi_tx: Fixed data bus width
2016-05-05 13:26:59 +03:00
bdfa383622
library/axi_ad9361: tdd false paths
2016-05-04 13:42:12 -04:00
ef6c99ecab
library/axi_ad9361: hw component updates
2016-05-04 13:42:12 -04:00
3b5e44e37d
library/axi_ad9361: mmcm rst for plls
2016-05-04 13:42:12 -04:00
16a13b2023
library/axi_ad9361: add rst/locked to clock
2016-05-04 13:42:11 -04:00
1aac44b0d9
library: ad_*clk- rst/locked
2016-05-04 13:42:11 -04:00
d82ca5dc3c
library/common- altera variations
2016-05-04 13:42:11 -04:00
b6b68e9ab7
axi_jesd_gt: Split the constraint file
...
-split axi_jesd_gt_constr.xdc file in rx, tx and common constraint files
-updated tcl script
2016-05-04 19:32:06 +03:00
583bafd17a
axi_ad7616: Add a new register for IF_TYPE
...
Add an additional new read only register at 0x03 address for the interface type. This way the software can verify the actual interface mode.
2016-05-04 16:14:29 +03:00
385ed31a45
make files update
2016-04-29 10:17:35 -04:00
3f5e1e1203
ad9361- dev_if module name change
2016-04-29 10:17:35 -04:00
89f5d2394e
altera- clock variations
2016-04-29 10:17:35 -04:00
243d3e6e41
ad9361- a10soc sdc files
2016-04-29 10:17:35 -04:00
aa2aa902bf
ad9361- a10soc updates
2016-04-29 10:17:35 -04:00
f411d29e30
ad9361- a10soc changes
2016-04-29 10:17:35 -04:00
3563c2212c
common/altera- removed dcfilt/mul
2016-04-29 10:17:35 -04:00
0260280db1
common/altera- data path
2016-04-29 10:17:35 -04:00
ed62101308
common/altera: primitives
2016-04-29 10:17:35 -04:00
779d014750
ad9361-common alt/xil interface
2016-04-29 10:17:35 -04:00
7ec4c00f9f
axi_ad7616: DMA is always ready
2016-04-29 16:36:33 +03:00
427f85959c
axi_ad7616: Fix the AXI stream interface
2016-04-29 16:34:34 +03:00
33199263e1
axi_ad7616: Delete burst_length register
...
This was an unnecessary feature of the hdl core.
2016-04-29 16:28:48 +03:00
d5d7c12f0e
axi_ad7616: Fix the register map
2016-04-25 11:36:39 +03:00
2ccdd426ec
axi_ad7616: Fix the rd_db_valid generation and do some cosmetic changes.
2016-04-25 11:28:22 +03:00
ad227c1af0
up_axi: Wait more to a valid read acknowledge.
2016-04-25 10:34:17 +03:00
e9b199959a
library/adcfifo- constraints update
2016-04-20 15:57:25 -04:00
679d471d75
Merge branch 'hdl_2016_r1' into dev
...
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
d7d8b2cf1c
axi_usb_fx3: Integrated actual GPIF II interface, with 2 address lines
2016-04-19 14:38:26 +03:00
e855ef38f4
axi_dacfifo: Initial commit
...
AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 11:28:33 +03:00
42cd05ab19
ad_mem_asym: Add support for more ratios.
...
Supported ratios: 1:1/1:2/1:4/1:8/2:1/4:1/8:1
2016-04-19 11:18:30 +03:00
6fe41ebb08
axi_hdmi_tx: Upgrade hdmi clipping process
...
-added two registers that control the clipping ranges (0x01a and 0x01b)
-extend clipping process for all output data formats
2016-04-12 22:01:07 +03:00
69d721526a
util_dacfifo: Add constraints file
2016-04-12 13:21:50 +03:00
255b0ebd40
util_dacfifo: Add dac_xfer_out control
...
The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
2016-03-29 16:50:00 +03:00
b31cdac6bd
util_gmii_to_rgmii: Updated to 2015.4
...
The Xilinx interface changed its name from gmii_rtl_1 to gmii_rt_1
2016-03-23 10:14:18 +02:00
46eddd04be
library: port updates on mmcm
2016-03-22 12:50:59 -04:00
de4da6726b
axi_clkgen: port updates on mmcm
2016-03-22 12:50:59 -04:00
74408881c6
axi_ad9122: optional clock out control
2016-03-22 12:50:59 -04:00
65b2e51958
common/mmcm: add another clock
2016-03-22 12:50:59 -04:00
769fecbe00
axi_i2s_adi: Fixed clock association
2016-03-21 20:18:45 +02:00
373481360b
util_dacfifo: Add a bypass option to the FIFO
2016-03-21 14:14:43 +02:00
6d277733d5
axi_spdif_rx: Fixed the clock association
2016-03-18 13:58:13 +02:00
28990e362a
axi_spdif_tx: Fixed the clock association
2016-03-18 13:31:06 +02:00
896c734792
Revert "foobar"
...
This reverts commit a3cb8cac45
2016-03-18 13:23:02 +02:00
a3cb8cac45
foobar
2016-03-18 11:51:13 +02:00
665bfbc991
axi_ad7616: Add M_AXIS_READY_ENABLE parameter
...
m_axis_ready can be driven by the DMA or can have a constant active state. By default is always one.
2016-03-15 18:38:55 +02:00
9b2a106aa0
axi_jesd_gt: changed clock and reset naming to be consistent with the other projects
2016-03-15 11:20:31 +02:00
06b7916303
axi_spdif_tx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:18:25 +02:00
ef05642e26
axi_spdif_rx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:14:05 +02:00
b3ed38107c
axi_i2s_adi: changed adi_ip_properties lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:12:45 +02:00
8ecf5edaf8
ad9122- pat modes
2016-03-14 11:14:29 -04:00
31cc91d1b9
adi_ip: Updated to 2014.4.2
...
- automatically infer clocks, resets, axim_mm and axis interfaces
2016-03-14 15:14:18 +02:00
33b265a742
Makefile: Update Makefiles
2016-03-14 09:31:17 +02:00
573146aa96
axi_ad7616: Fix the data width of the AXI stream interface
2016-03-10 16:38:53 +02:00
287770a201
axi_dmac: Fix tlast generation on AXI stream master
...
For the AXI stream interface we want to generate TLAST only at the end of
the transfer, rather than at the end of each burst.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-03-08 10:53:59 +01:00
2524f19ae0
Updated interfaces Makefile and Makefiles for the libraries that depend on it
2016-03-07 12:31:41 +02:00
583ef82fd0
ad9361- cmos mode
2016-03-04 10:39:48 -05:00
7a320a3d34
ad_lvds* - updates
2016-03-04 10:39:48 -05:00
7d2939be92
ad9361- cmos mode initial commit
2016-03-04 10:39:48 -05:00
377461e0d4
Merge branch 'hdl_2015_r2' into dev
2016-02-19 14:15:27 +02:00
a8e9d72273
adc/dac - prefix parameters
2016-02-17 14:16:04 -05:00
e1c5d6a8f7
axi_ad9684: Fix constraint file
2016-02-12 14:38:59 +02:00
a747fad540
axi_ad9361: tx_valid must be controlled by the TDD controller
2016-02-12 14:33:34 +02:00
e381d5170c
util_tdd_sync: Update the synchronization interface
...
Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-12 14:27:37 +02:00
0d67af370f
util_upack: Fixed problem when dac valid isn't continuous from the DAC
...
In cases when the dac_valid_ from the DAC is not continuous, in some situations
there were two dac_valid pulses sent to the DMA.
2016-02-04 13:03:46 +02:00
3d3d1098b4
axi_ad7616: Default DATA_WIDTH is 8 bits
2016-01-28 16:02:01 +02:00
122667259f
ad7616_sdz: Update Make file
2016-01-28 14:48:44 +02:00
fbb0d368bf
axi_ad7616: Add support for parallel interface
2016-01-28 12:37:22 +02:00
cd43ebd8bc
axi_ad7616: The OP_MODE parameter is no longer required
2016-01-26 11:05:33 +02:00
2a17ce275c
axi_ad7616: Control inputs are controlled through GPIO
...
The following control inputs are controlled through GPIO: reset_n, seq_en, hw_rngsel, chsel, crcen, burst and os.
2016-01-25 17:50:50 +02:00
4b962e8d72
spi_engine: The width of the counters depend on the current DATA_WIDTH
2016-01-20 15:44:06 +02:00
4cc69c0cac
axi_ad9684: Add Makefile
2016-01-19 18:32:11 +02:00
c865dbf353
axi_ad9680: Fix channel instantiation
2016-01-19 12:49:45 +02:00
df3eefdca1
axi_ad9434: Update constraint file
2016-01-19 12:43:05 +02:00
d1e638349b
ad_serdes_clk : The reference clock selection line should by tied to 1
...
Just the CLKIN1 is used in the MMCM.
2016-01-19 11:18:00 +02:00
c6cfd1a2b6
axi_ad9684: Initial check in
2016-01-19 11:13:45 +02:00
4f2b999999
axi_ad9680: Q_OR_I_N is not used in this channel
2016-01-13 16:26:22 +02:00
838b558176
axi_ad9434: Fix adc_status
...
adc_status was not driven by anything. Should be driven by adc_status_m1.
2016-01-13 12:21:42 +02:00
2dcd9136aa
axi_ad6676: Delete confusing comment
2016-01-13 10:20:18 +02:00
c29dd8fad5
axi_ad7616: Fix Makefile
2015-12-21 19:39:58 +02:00
0b55325db9
axi_ad7616: Fix IP packaging script
2015-12-21 19:39:14 +02:00
17e7d1b86f
ad7616: Add Makefiles
2015-12-21 17:09:42 +02:00
8ae9de8fba
axi_ad7616: Update core
...
+ Both the data width and number of SDI lines are configurable
+ SER1W line is hardware configurable, it was removed from the IP
+ Add 'Hardware mode' support for the controller
2015-12-14 16:00:56 +02:00
Rejeesh Kutty
Adrian Costina
Istvan Csomortani
AndreiGrozav
Lars-Peter Clausen
Dragos Bogdan
Shrutika Redkar
Matthew Fornero
István Csomortáni