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5616 Commits (144fcc2965031008629ac8abe722b856fe6a9a74)

Author SHA1 Message Date
Adrian Costina 144fcc2965 adrv9009: Fix typo for number of samples calculation for observation channel 2020-09-25 11:58:58 +03:00
Adrian Costina bde2d1d66d fmcomms8: zcu102: Leave the SPI constraint at 25 MHz 2020-09-25 11:54:12 +03:00
Adrian Costina 4d2e05d5dd fmcomms8: common: In the SPI module, use ad_iobuf instead of a Xilinx primitive 2020-09-25 11:54:12 +03:00
Adrian Costina f8c2eb12d4 fmcomms8: zcu102: Remove the test pins, as they are not connected 2020-09-25 11:54:12 +03:00
stefan.raus d2ef1bcef5 library/commmon: Fix data width warnings 
ad_tdd_control.v: Set ON and OFF local parameters on just one bit.
up_dac_common.v: Set CLK_EDGE_SEL parameter on just one bit.
 2020-09-23 09:16:48 +03:00
stefan.raus 1e31b9dd97 arradio: Remove unused signals 
Remove 'ad9361_clk_out' since is not used anymore, fixing in this way 'Warning (21074): Design contains 1 input pin that do not drive logic'
 2020-09-23 09:16:48 +03:00
sergiu arpadi f2f6422751 sysid: Fix board/project name underscore issue 2020-09-17 10:32:58 +03:00
AndreiGrozav 6ae822d42c cn0506_rmii: Fix no defined clock warnings 2020-09-16 10:57:15 +03:00
Istvan Csomortani 49d4286459 cn0540/de10nano: Delete GPIO connection to DRDY 2020-09-15 18:14:23 +03:00
Istvan Csomortani 4838ac0ac2 cn0540/coraz7s: Time the SPI interface of AD7768-1 2020-09-15 18:14:23 +03:00
AndreiGrozav 0933949ad7 adv7513: Add initial project for de10nano 2020-09-15 18:14:23 +03:00
Stanca Pop 043ddbaf9f cn0540: Add de10nano reference design 2020-09-15 18:14:23 +03:00
Istvan Csomortani ad8d2d225f de10: Delete redundant base design 2020-09-15 18:14:23 +03:00
Stanca.Pop fd1c3c7cdd common/de10nano: Add de10nano base design 2020-09-15 18:14:23 +03:00
Stanca Pop 6cea8ce777 adi_project_intel: Add de10nano support 2020-09-15 18:14:23 +03:00
Istvan Csomortani cba3c0f4f1 spi_engine_offload: Define status_sync interface 2020-09-15 18:14:23 +03:00
Istvan Csomortani 780579f3e9 spi_engine_offload: Delete trailing whitespaces 2020-09-15 18:14:23 +03:00
Istvan Csomortani b827322917 spi_engine_execution: Add missing parameter definition into hw.tcl script 2020-09-15 18:14:23 +03:00
Istvan Csomortani f67209e125 axi_spi_engine: Fix the hw.tcl script 
Define both AXI4 Memory Mapped and microprocessor interface for the
reigster map, then activate/deactive one of it in fucntion of the memory
interface type parameter.

Define the missing status_sync interface, which should be connected to
the offload.
 2020-09-15 18:14:23 +03:00
Istvan Csomortani f934ff7e4e axi_spi_engine: Add missing ports to every sub-module instance 2020-09-15 18:14:23 +03:00
Istvan Csomortani a5326cb3d2 axi_spi_engine: Refactoring sdi_fifo read outs 
Context switching with a parameter is not a good idea. The simulator
may evaluate both branch of the IF statement, even though the inactive
branch may not be valid.

Use if..generate to make the code more robust for both synthesizers and
simulators.
 2020-09-15 18:14:23 +03:00
AndreiGrozav 422d7c949c axi_hdmi_tx_vdma: Use only synchronous reset 2020-09-15 18:14:23 +03:00
AndreiGrozav 520a7ea972 axi_hdmi_tx: Update IP to latest HDL flow 
Conflicts:
	library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl
 2020-09-15 18:14:23 +03:00
AndreiGrozav 585ed44983 Add 'SE Base' family to the supported FPGAs 2020-09-15 18:14:23 +03:00
Istvan Csomortani 40772a8b2c ad40xx_fmc/zed: Fix constraints, to avoid critical warnings in synthesis 2020-09-15 13:08:39 +03:00
Istvan Csomortani 85aeb915b4 spi_engine_offload: Start offload when DMA is ready 2020-09-15 12:03:48 +03:00
Istvan Csomortani 121ac2e97a spi_engine_interconnect: always construct must not contains mixed assignment types 2020-09-15 12:01:58 +03:00
Sergiu Arpadi 3241924d14 sysid_intel: Added sysid to intel projects 2020-09-11 15:46:06 +03:00
Sergiu Arpadi f57643b451 sysid_intel: Added adi_pd_intel.tcl 2020-09-11 15:46:06 +03:00
Arpadi 4a28a4e856 sysid_intel: Added hw.tcl for sysid IP cores 2020-09-11 15:46:06 +03:00
AndreiGrozav 1e537b1083 axi_ad9963: Fix warnings 
-fix missing connection warnings
-fix wrong bus width warning
 2020-09-11 10:24:22 +03:00
AndreiGrozav 3d407a3ba5 axi_ad9467: Fix missing connection warnings 2020-09-11 10:24:22 +03:00
AndreiGrozav 5f0abc5099 axi_ad9361: Fix missing connection warnings 2020-09-11 10:24:22 +03:00
AndreiGrozav f2422080de axi_hdmi_tx: Fix warning on imageon 
Remove an extra assignment to hdmi_vs register.
 2020-09-11 10:23:53 +03:00
AndreiGrozav 498e07e640 ad_csc: Fix warning for axi_hdmi_tx 
Converting from RGB to YCbCr takes one less stage than converting
from YCbCr to RGB color space.
Moving extra delay stage(5), of the sync signals to a particular
YCbCr to RGB color space conversion case.
 2020-09-11 10:23:53 +03:00
AndreiGrozav f0a29a682f common/ad_ss_422to444.v: Fix warning 
Using a localparam in a port declaration, causes the following warning:
"identifier 'DW' is used before its declaration".
 2020-09-11 10:23:53 +03:00
AndreiGrozav 0152b645a6 m2k: Fix Warnings 
Fix warnings caused by attempting to set a value to a disabled parameter.
 2020-09-11 10:23:26 +03:00
AndreiGrozav 8d80b0f85f axi_logic_analyzer: Fix data width warning 2020-09-11 10:23:26 +03:00
Istvan Csomortani 9ee0f09078 daq3:qsys: Activate input pipeline stage for AD9680's JESD interface 2020-09-09 14:15:37 +03:00
Dragos Bogdan c8e0a1ec04 projects: adrv9009: intel: Update JESD204 LANE_RATE and REFCLK_FREQUENCY 
To match the Linux default setup.

Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
 2020-09-09 14:15:37 +03:00
Istvan Csomortani 61ece1f1e9 s10soc: Insert an additional bridge between DMA and HPS 
Due to the interface differences between HPS's AXI4 and DMA's AXI4, the
tool will try to automaticaly add some bridges between the two
interface. Unfortunatly it does generate timing issues at the f2sdram0
interface of the HPS instance. By explicitly instantiating an AXI
bridge, these timing issues disappears.
 2020-09-09 14:15:37 +03:00
Istvan Csomortani 1e5e859222 intel/axi_adxcvr: Use ad_ip_files process for source definition 2020-09-09 14:15:37 +03:00
Istvan Csomortani 46b6bf8f8a adrv9009/qsys: input pipline active for jesd204_rx and jesd204_rx_os 2020-09-09 14:15:37 +03:00
Istvan Csomortani 256593623c intel/adi_jesd204: Add an additional pipeline stage to RX soft PCS 2020-09-09 14:15:37 +03:00
Istvan Csomortani 0e98527bad intel/adi_jesd204: Expose REGISTER_INPUTS parameter 
Define INPUT_PIPELINE parameter, which can be used to activate the
REGISTER_INPUTS parameter of the PHY. This parameter will add an
additional register stage into the incoming parallel data stream.
It can be used to relax the timing margin between the PHY and Link modules.
 2020-09-09 14:15:37 +03:00
Istvan Csomortani 72a4d54b76 jesd204_rx: Fix SDC constraint 2020-09-09 14:15:37 +03:00
Istvan Csomortani 5a8f277253 adrv9009/s10soc: Add support for Stratix10 SOC 2020-09-09 14:15:37 +03:00
Istvan Csomortani 2b5136db98 scripts/project_intel.mk: Update CLEAN targets 2020-09-09 14:15:37 +03:00
Istvan Csomortani eb8e1142cd adrv9009/intel: Fix the register address layout 
The reconfiguration interface for the Stratix10 XCVR has a different
address width. Prepare the register map layout of the project to support
this new architecture.
 2020-09-09 14:15:37 +03:00
Istvan Csomortani 8818089015 a10soc: Reconfiguration interface address width improvement 
The reconfiguration interface's address width is different in various
architectures. Define the required address width in system_qsys.tcl.
 2020-09-09 14:15:37 +03:00