144fcc2965
adrv9009: Fix typo for number of samples calculation for observation channel
2020-09-25 11:58:58 +03:00
bde2d1d66d
fmcomms8: zcu102: Leave the SPI constraint at 25 MHz
2020-09-25 11:54:12 +03:00
4d2e05d5dd
fmcomms8: common: In the SPI module, use ad_iobuf instead of a Xilinx primitive
2020-09-25 11:54:12 +03:00
f8c2eb12d4
fmcomms8: zcu102: Remove the test pins, as they are not connected
2020-09-25 11:54:12 +03:00
1e31b9dd97
arradio: Remove unused signals
...
Remove 'ad9361_clk_out' since is not used anymore, fixing in this way 'Warning (21074): Design contains 1 input pin that do not drive logic'
2020-09-23 09:16:48 +03:00
f2f6422751
sysid: Fix board/project name underscore issue
2020-09-17 10:32:58 +03:00
6ae822d42c
cn0506_rmii: Fix no defined clock warnings
2020-09-16 10:57:15 +03:00
49d4286459
cn0540/de10nano: Delete GPIO connection to DRDY
2020-09-15 18:14:23 +03:00
4838ac0ac2
cn0540/coraz7s: Time the SPI interface of AD7768-1
2020-09-15 18:14:23 +03:00
0933949ad7
adv7513: Add initial project for de10nano
2020-09-15 18:14:23 +03:00
043ddbaf9f
cn0540: Add de10nano reference design
2020-09-15 18:14:23 +03:00
ad8d2d225f
de10: Delete redundant base design
2020-09-15 18:14:23 +03:00
fd1c3c7cdd
common/de10nano: Add de10nano base design
2020-09-15 18:14:23 +03:00
6cea8ce777
adi_project_intel: Add de10nano support
2020-09-15 18:14:23 +03:00
40772a8b2c
ad40xx_fmc/zed: Fix constraints, to avoid critical warnings in synthesis
2020-09-15 13:08:39 +03:00
3241924d14
sysid_intel: Added sysid to intel projects
2020-09-11 15:46:06 +03:00
f57643b451
sysid_intel: Added adi_pd_intel.tcl
2020-09-11 15:46:06 +03:00
0152b645a6
m2k: Fix Warnings
...
Fix warnings caused by attempting to set a value to a disabled parameter.
2020-09-11 10:23:26 +03:00
9ee0f09078
daq3:qsys: Activate input pipeline stage for AD9680's JESD interface
2020-09-09 14:15:37 +03:00
c8e0a1ec04
projects: adrv9009: intel: Update JESD204 LANE_RATE and REFCLK_FREQUENCY
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To match the Linux default setup.
Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
2020-09-09 14:15:37 +03:00
61ece1f1e9
s10soc: Insert an additional bridge between DMA and HPS
...
Due to the interface differences between HPS's AXI4 and DMA's AXI4, the
tool will try to automaticaly add some bridges between the two
interface. Unfortunatly it does generate timing issues at the f2sdram0
interface of the HPS instance. By explicitly instantiating an AXI
bridge, these timing issues disappears.
2020-09-09 14:15:37 +03:00
46b6bf8f8a
adrv9009/qsys: input pipline active for jesd204_rx and jesd204_rx_os
2020-09-09 14:15:37 +03:00
5a8f277253
adrv9009/s10soc: Add support for Stratix10 SOC
2020-09-09 14:15:37 +03:00
2b5136db98
scripts/project_intel.mk: Update CLEAN targets
2020-09-09 14:15:37 +03:00
eb8e1142cd
adrv9009/intel: Fix the register address layout
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The reconfiguration interface for the Stratix10 XCVR has a different
address width. Prepare the register map layout of the project to support
this new architecture.
2020-09-09 14:15:37 +03:00
8818089015
a10soc: Reconfiguration interface address width improvement
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The reconfiguration interface's address width is different in various
architectures. Define the required address width in system_qsys.tcl.
2020-09-09 14:15:37 +03:00
91b199a907
s10soc: Add new feature for ad_cpu_interconnect
...
If we have a lot of peripherals connected to the CPU's memory interface,
the generated interconnect can grow to much decreasing the timing
margin.
One solution is to group the peripherals by its interface types and
functions and use bridges to connect them to the memory interface.
This commit adds the possibility to insert an Avalon Memory Mapped
bridge when we create the connection between the peripheral and CPU.
Should be used just with Avalaon Memory Mapped interfaces.
2020-09-09 14:15:37 +03:00
f9c4283f45
stratix10soc: Initial commit of base design
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Note: Currently we have a engineering sample version 2 board.
2020-09-09 14:15:37 +03:00
24090fafd8
adrv9001/zcu102: Loopback VADJ error to the FMC board
2020-08-31 14:14:03 +03:00
d14376547f
adrv9001/zed: Refactor VADJ test in VADJ error
...
The ADRV9002 uses in the digital interface 1.8V, however the Zed VADJ is
selectable by a jumper can go up to 3.3V . Voltage levels higher than 1.8V
are detected by the EVAL-ADRV9002 board, asserting the VADJ_ERR pin.
If VADJ error is set high keep all drivers in high-z state and signalize
it to the software layer through a gpio line.
2020-08-31 14:14:03 +03:00
72f916fcf5
adrv9001/zcu102: Update interface signal names based on direction
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Let the names of signals from source synchronous interface match the
direction of the signals.
2020-08-28 13:23:00 +03:00
a212ad6e58
adrv9001/zed: Update interface signal names based on direction
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Let the names of signals from source synchronous interface match the
direction of the signals.
2020-08-28 13:23:00 +03:00
eb2f211d30
scripts/intel: Add message severity definition file
2020-08-25 14:46:52 +03:00
9c4df588bb
fmcomms2: a10soc remove project
...
Starting from Quartus 18.1 the project won't build as LVDS SERDES needs to be
driven by a dedicated reference clock pin and A10SOC doesn't have dedicated pins
routed at the _CC FMC location.
Prior to version 18.0 this was reported as a critical warning.
See https://community.intel.com/t5/Intel-Quartus-Prime-Software/LVDS-SERDES-reference-clock-enforcement-change-in-18-1/td-p/196078
2020-08-25 14:19:48 +03:00
118e1f9e8b
adrv9001/zed: Initial support for Zed
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CMOS only support for ADRV9001 on ZedBoard
2020-08-24 17:49:12 +03:00
b27f3ac18f
adrv9001:zcu102: Initial version
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Generic project that supports CMOS or LVDS interface for the ADRV9001 transceiver.
2020-08-24 17:49:12 +03:00
d8c98c9904
cn0540/coraz7s: Relax timing in SPI Engine
2020-08-24 16:45:02 +03:00
fa0b39fa20
adi_project_intel: Update QSYS generation
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In Quartus Prime in place of the set_domain_assignment command, the
set_interconnect_requirement command is used.
2020-08-17 12:02:49 +03:00
b54effc9c9
daq2/a10gx: Set optimization mode to aggressive performance
2020-08-17 10:43:03 +03:00
fb7da01498
adrv9371x/a10gx: Set optimization mode to aggressive performance
2020-08-17 10:43:03 +03:00
738f7af23b
ad40xx_fmc: SDI delay should be set to 1
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In general we have to add a delay of half SCLK cycle.
(latch the MISO on the next consecutive SCLK edge)
2020-08-13 10:01:16 +03:00
4766d01915
m2k: Update constraints
2020-08-13 07:01:19 +03:00
4d39a3595f
m2k: Connect signals for instrument sync
2020-08-13 07:01:19 +03:00
f3b69c15c9
scripts/intel: Update version check
2020-08-12 10:33:29 +03:00
218f45a0df
scripts/intel: Set supported Quartus version to 19.3
2020-08-12 10:33:29 +03:00
62eb5a067d
fmcomms2/a10soc: Unused outputs should be left hanging
2020-08-11 10:14:18 +03:00
a66029aef3
adrv9009/a10gx: Delete redundant timing constraints
2020-08-11 10:14:18 +03:00
02ada3bbf7
a10gx: Delete input/output delay definitions
...
All input and output delays should be referenced to a virtual clock.
If the input and output delays reference base clocks or PLL clocks rather than
virtual clocks, the intra- and inter-clock transfer clock uncertainties,
determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports.
See mnl_timequest_cookbook.pdf for more info.
2020-08-11 10:14:18 +03:00
f1a0946a5d
daq3: Delete redundant timing constraint
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Delete none generic timing constarints related to the memory interface.
Set optimization mode to default.
2020-08-11 10:14:18 +03:00
1c907b9248
daq2/a10gx: Use the default optimization mode
2020-08-11 10:14:18 +03:00
Adrian Costina
stefan.raus
sergiu arpadi
AndreiGrozav
Istvan Csomortani
Stanca Pop
Stanca.Pop
Dragos Bogdan
Laszlo Nagy