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3012 Commits (14ad1ea74190a77daaff7a7a8f87000acf5d182f)

Author SHA1 Message Date
Rejeesh Kutty d7f0bd1b76 ad9361- add reset sink 2016-05-18 13:24:13 -04:00
Rejeesh Kutty bb4ed42a93 ad9361- add missing wires 2016-05-18 13:24:13 -04:00
AndreiGrozav 42b0fabd40 axi_hdmi_tx_core: Fixed data path 2016-05-17 14:41:18 +03:00
Rejeesh Kutty e345953bdd arradio- updates 2016-05-16 12:19:38 -04:00
Rejeesh Kutty 68329de738 ad9361- interface updates 2016-05-16 12:19:38 -04:00
Rejeesh Kutty 421c0519f4 util_rfifo- updates 2016-05-16 12:19:38 -04:00
Rejeesh Kutty e05204a86d util_cpack: interface updates 2016-05-16 12:19:38 -04:00
Rejeesh Kutty 6bc05fc844 ad_*_in: register post-iob 2016-05-16 12:19:38 -04:00
Rejeesh Kutty cd7c9c99ed ad_*_clk: altera-pll not supported by qsys flow 2016-05-16 12:19:38 -04:00
Rejeesh Kutty 4fbff45e27 util_wfifo- updates 2016-05-16 12:19:38 -04:00
Rejeesh Kutty f515885fc4 util_wfifo: altera ip 2016-05-16 12:19:38 -04:00
Rejeesh Kutty 58a2a3259c util_rfifo: updates 2016-05-16 12:19:38 -04:00
Rejeesh Kutty 82d43783f1 util_rfifo: altera ip 2016-05-16 12:19:38 -04:00
Rejeesh Kutty 31671bf9d5 util_rfifo: constraints 2016-05-16 12:19:38 -04:00
Adrian Costina 72151bb1a6 a10gx: Updated base design to include MMU 2016-05-13 18:44:41 +03:00
Rejeesh Kutty f3f5353944 zcu102- updates 2016-05-10 15:40:41 -04:00
Rejeesh Kutty 16e3a0e569 zcu102- updates 2016-05-10 15:40:41 -04:00
Rejeesh Kutty aadb220a3f zcu102- updates 2016-05-10 15:40:41 -04:00
Rejeesh Kutty e1350018da zcu102- updates 2016-05-10 15:40:41 -04:00
Rejeesh Kutty a6411dbd63 zcu102- added 2016-05-10 15:40:41 -04:00
Rejeesh Kutty e8fbdd0f5d zcu102: zynq ultrascale 2016-05-10 15:40:41 -04:00
Rejeesh Kutty 0041bf69be c5soc- remove unused hps ports 2016-05-09 13:54:08 -04:00
Rejeesh Kutty 89b20f2a35 c5soc- remove unused hps ports 2016-05-09 13:54:08 -04:00
Rejeesh Kutty 3871d3ce2b ad9361-c5/a10 - updates 2016-05-09 13:54:08 -04:00
Rejeesh Kutty 9cd6e2da51 quartus-mess- altddio direct instantiation 2016-05-09 13:54:08 -04:00
AndreiGrozav 726ddb6e93 ad_lvds_clk: Fixed assignment mismatched 2016-05-09 10:32:18 +03:00
AndreiGrozav 8d72b645ae fmcomms2/common: Remove ila_tdd block 2016-05-09 10:28:10 +03:00
Istvan Csomortani b0538a03a2 Make: Update 2016-05-06 16:44:24 +03:00
AndreiGrozav b36c722ec9 up_hdmi_tx: Discard the standard default values 
Restore the base functionality of the core. Changing the data format
will not set by default its standard maximum and minimum data clipping
ranges.
 2016-05-05 13:41:46 +03:00
AndreiGrozav 68d83def01 axi_hdmi_tx_core: Fixed data path 2016-05-05 13:32:25 +03:00
AndreiGrozav 0d2dc2c62b axi_hdmi_tx: Fixed data bus width 2016-05-05 13:26:59 +03:00
Istvan Csomortani 4863a04132 axi_adc/dacfifo: Split the intergration script file 
Split the integration script file into two separate script files. Rename the
integration processes names to be more meaningful.
 2016-05-05 09:53:55 +03:00
Rejeesh Kutty ddfaff2cf5 fmcomms2/a10soc: compile version 2016-05-04 13:42:12 -04:00
Rejeesh Kutty f4e5965936 fmcomms2/a10soc: ip updates 2016-05-04 13:42:12 -04:00
Rejeesh Kutty 92dcce1674 a10soc: default ports 2016-05-04 13:42:12 -04:00
Rejeesh Kutty bdfa383622 library/axi_ad9361: tdd false paths 2016-05-04 13:42:12 -04:00
Rejeesh Kutty ef6c99ecab library/axi_ad9361: hw component updates 2016-05-04 13:42:12 -04:00
Rejeesh Kutty 3b5e44e37d library/axi_ad9361: mmcm rst for plls 2016-05-04 13:42:12 -04:00
Rejeesh Kutty 16a13b2023 library/axi_ad9361: add rst/locked to clock 2016-05-04 13:42:11 -04:00
Rejeesh Kutty 1aac44b0d9 library: ad_*clk- rst/locked 2016-05-04 13:42:11 -04:00
Rejeesh Kutty d82ca5dc3c library/common- altera variations 2016-05-04 13:42:11 -04:00
AndreiGrozav be74db656c ad6674evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1: 
Update system_project.tcl scripts to correctly select the necessary
constraint files
 2016-05-04 19:37:33 +03:00
AndreiGrozav b6b68e9ab7 axi_jesd_gt: Split the constraint file 
-split axi_jesd_gt_constr.xdc file in rx, tx and common constraint files
-updated tcl script
 2016-05-04 19:32:06 +03:00
AndreiGrozav 3ca3414522 fmcadc2: Fixed bus data width 2016-05-04 19:20:01 +03:00
AndreiGrozav 9104b2cc60 ad6676evb, fmcadc2, fmcadc4, fmcadc5,... 
ad6676evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1: Remove unused
set_proprieties
 2016-05-04 19:13:25 +03:00
István Csomortáni 583bafd17a axi_ad7616: Add a new register for IF_TYPE 
Add an additional new read only register at 0x03 address for the interface type. This way the software can verify the actual interface mode.
 2016-05-04 16:14:29 +03:00
Rejeesh Kutty 385ed31a45 make files update 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 3f5e1e1203 ad9361- dev_if module name change 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 61b531b1c1 a10soc device update 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 89f5d2394e altera- clock variations 2016-04-29 10:17:35 -04:00