Commit Graph

3986 Commits (1541943ff22e9c15ae21c865aa25f6e4b0c324fa)

Author SHA1 Message Date
Istvan Csomortani 1541943ff2 adrv9371_alt: Delete the fifos from the RX path
+ Delete the rx_fifo and rx_os_fifo from the RX datapath
  + Change the receive DMA's source interface type to wr_fifo
2017-06-22 11:58:10 +01:00
Rejeesh Kutty 354b311f3d library/avl_adxcvr: fpll fixes 2017-06-21 15:26:00 -04:00
Lars-Peter Clausen 94586a5b49 jesd204: tb: Fix signal width mismatch warnings
Always explicitly specify the signal width for constants to avoid warnings
about signal width mismatch.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Lars-Peter Clausen 885b364a46 jesd204: rx_static_config: Set RBD to 0
The buffer delay should be 0 in the default configuration. The current
value of 0xb must have slipped in by accident.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Lars-Peter Clausen 71cc052825 jesd204: rx: Use standalone counter for lane latency monitor
Use a single standalone counter that counts the number of beats since the
release of the SYNC~ signal, rather than re-using the LMFC counter plus a
dedicated multi-frame counter.

This is slightly simpler in terms of logic and also easier for software to
interpret the data.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Lars-Peter Clausen 9e50f5afa8 jesd204: Handle sysref events in the register map
There are currently two sysref related events. One the sysref captured
event which is generated when an external sysref edge has been observed.
The other is the sysref alignment error event which is generated when a
sysref edge is observed that has a different alignment from previously
observed sysref edges.

Capture those events in the register map. This is useful for error
diagnostic. The events are sticky and write-1-to-clear.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Lars-Peter Clausen d3b44906c3 jesd204: Properly align LMFC offset in register map
The internal LMFC offset signals are in beats, whereas the register map is
in octets. Add the proper alignment padding to the register map to
translate between the two.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Lars-Peter Clausen baa256e34c jesd204: Slightly rework sysref handling
For SYSREF handling there are now three possible modes.

1) Disabled. In this mode the LMFC is generated internally and all external
SYSREF edges are ignored. This mode should be used for subclass 0 when no
external sysref is available.
2) Continuous SYSREF. An external SYSREF signal is required and the LMFC is
aligned to the SYSREF signal. The SYSREF signal is continuously monitored
and if a edge unaligned to the previous edges is detected the LMFC is
re-aligned to the new edge.
3) Oneshot SYSREF. Oneshot SYSREF mode is similar to continuous SYSREF mode
except only the first edge is captured and all further edges are ignored,
re-alignment will not happen.

Both in continuous and oneshot signal at least one external sysref edge is
required before an LMFC is generated. All events that require an LMFC will
be delayed until a SYSREF edge has been captured. This is done to avoid
accidental re-alignment.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Lars-Peter Clausen bf88527119 library: jesd204: jesd204_up_common: Fix indention
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Lars-Peter Clausen 2e8be3d7a6 daq2: Provide DAC lane map
Provide the correct lane mapping for the DAQ2 DAC lanes which do not follow
a 1-to-1 mapping between physical and logical lanes due to PCB layout
constraints.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Lars-Peter Clausen 4bf5990451 adi_board.tcl: ad_xcvrcon: Add lane mapping support
Add a parameter to the ad_xcvrcon function that allows to provide a mapping
between logical and physical lanes. By default if no lane map is provided
the logial and physical lanes are mapped 1-to-1. If a lane map is provided
logical lane $n is mapped onto physical lane $lane_map[$n].

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Lars-Peter Clausen 9f954303ac up_clock_mon: Fix stopped clock detection logic
A broken version of the stopped clock detection logic was merged by
accident. Fix it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Istvan Csomortani f415b4f973 axi_ad5766: Delete unused interface definition 2017-06-20 11:55:10 +01:00
Adrian Costina 871855c9ec axi_logic_analyzer: Fix delayed trigger assertion condition 2017-06-19 10:58:22 +03:00
Matthew Fornero d840baee28 util_clkdiv: Register output port as a clock (#33)
If the output pin is not defined as a clock, some of the Vivado IPI
propagation TCL will error out.

Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
2017-06-19 07:52:43 +01:00
Rejeesh Kutty dc94dd3ea7 jesd204- apply constraints after top 2017-06-16 15:30:18 -04:00
Rejeesh Kutty 513f6ae18a adi_ip.tcl- general rule- order independent constraints 2017-06-16 13:51:35 -04:00
Rejeesh Kutty 56867b362e daq3- updated to 12.5G 2017-06-16 09:02:26 -04:00
Rejeesh Kutty 3fb5408acc fmcjesdadc1/a10gx- fix sysref, lvds io and such 2017-06-15 13:57:21 -04:00
Rejeesh Kutty 6ec9eab7b9 fmcjesdadc1/a10soc- fix sysref, lvds io and such 2017-06-15 13:57:21 -04:00
Rejeesh Kutty ef290ef484 hdlmake.pl updates 2017-06-15 11:42:44 -04:00
Rejeesh Kutty e33e6a84f4 a5gt/a5soc - removed 2017-06-15 11:41:28 -04:00
Rejeesh Kutty a23fb793a0 a5gt/a5soc - removed 2017-06-15 11:40:58 -04:00
Rejeesh Kutty 9e2d55ed07 adi_ip_alt: allow composition only parameter settings 2017-06-15 11:36:39 -04:00
Rejeesh Kutty 9464f342cf avl_adxcvr: remove arria v support 2017-06-15 11:36:14 -04:00
Rejeesh Kutty 2649458b6d hdlmake.pl updates 2017-06-15 10:21:57 -04:00
Rejeesh Kutty fd0c7f1b1c usdrx1/a10gx- updated to a10gx 2017-06-15 10:21:57 -04:00
Rejeesh Kutty 0311ed411c usdrx1/a10gx- added 2017-06-15 10:21:57 -04:00
Rejeesh Kutty 7ac083b932 fmcjesdadc1/a10soc- sysref fixes 2017-06-15 10:15:59 -04:00
Rejeesh Kutty 004aee930b fmcjesdadc1/a10gx- fix sysref, gpio connections 2017-06-14 14:40:23 -04:00
Rejeesh Kutty dba419239b hdlmake.pl updates 2017-06-14 10:41:14 -04:00
Rejeesh Kutty 3299d244fe fmcjesdadc1: a10gx/a10soc 2017-06-14 10:39:57 -04:00
Rejeesh Kutty 38c708d4d0 fmcjesdadc1: a10gx/a10soc 2017-06-14 10:39:38 -04:00
Rejeesh Kutty 051c1d6644 fmcjesdadc1: a10soc 2017-06-13 15:00:22 -04:00
Rejeesh Kutty c1bc1259a7 fmcjesdadc1: a10gx 2017-06-13 12:39:45 -04:00
Rejeesh Kutty 3f3ea5f99a hdlmake.pl- updates 2017-06-13 09:55:08 -04:00
Rejeesh Kutty ffb6cd4b0b scripts- add a5soc device 2017-06-13 09:54:01 -04:00
Rejeesh Kutty ff646b0cfc common/a5soc- alt 16.1 updates 2017-06-13 09:54:01 -04:00
Rejeesh Kutty 0eacde9158 fmcjesdadc1/a5soc- alt 16.1 updates 2017-06-13 09:54:01 -04:00
Adrian Costina 2fc5d08c0b axi_gpreg: Fixed constraints 2017-06-13 14:04:43 +03:00
Rejeesh Kutty 6decba3c3b hdlmake.pl updates 2017-06-09 16:23:17 -04:00
Rejeesh Kutty 173837f5b2 altera- altera ip interfaces has no consistency 2017-06-09 16:21:44 -04:00
Rejeesh Kutty 74f9a99655 fmcjesdadc1/a5gt- altera 16.1 updates 2017-06-09 16:20:49 -04:00
Rejeesh Kutty 2e17e67627 common/a5gt- altera 16.1 updates 2017-06-09 16:20:15 -04:00
Rejeesh Kutty 688758e6c6 scripts/adi_project_alt- add a5soc, a5gt 2017-06-09 16:19:29 -04:00
Rejeesh Kutty 227bd3edfe alt_ifconv-- qsys workaround 2017-06-09 16:17:34 -04:00
Rejeesh Kutty ca536d50ac altera 16.1 c5soc updates 2017-06-08 15:03:03 -04:00
Rejeesh Kutty f3af192f30 altera 16.1 arradio updates 2017-06-08 15:02:46 -04:00
Rejeesh Kutty ca20309166 adi_project_alt: add c5soc 2017-06-08 15:02:24 -04:00
Rejeesh Kutty 034aa7c1ee altera 16.1- recommends using fpll for dedicated low skew clock routing 2017-06-08 10:50:52 -04:00