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18 Commits (15e9c65c834118a003ee5795572bb8a35dea55e8)

Author SHA1 Message Date
LIacob106 e932e6f4f8 projects/adrv9009zu11eg: JESD support for fmcomms8 
for configurations 4, 8 TX_L and 4 RX/ORX_L

Signed-off-by: LIacob106 <liviu.iacob@analog.com>
 2023-01-26 15:38:38 +02:00
LIacob106 261c0d1b90 projects/adrv9009zu11eg: JESD support for adrv2crr_fmc 
for configurations 2, 4 TX_L and 2 RX/ORX_L

Signed-off-by: LIacob106 <liviu.iacob@analog.com>
 2023-01-26 15:38:38 +02:00
Liviu.Iacob 5350baffd0 adrv9009zu11eg/common/adrv9009zu11eg_bd: Add logic for TX_JESD_L=4 2022-10-03 10:27:33 +03:00
LIacob106 3e297f54dd projects/adrv9009zu11eg: expose jesd params to make and add FMCOMMS8 parameter 
Expose JESD parameters to make.
Add FMCOMMS8 parameter.
Changed the name of the observation path to match the rest of the repo.
Replace old dac_data_width formula with a more generic one.
 2022-09-26 14:26:31 +03:00
Laszlo Nagy 8ec657315c adrv9009zu11eg: Drive cpack/upack reset from TPL 2022-02-07 19:14:01 +02:00
Laszlo Nagy d949936a1b adrv9009zu11eg/common: EXT_SYNC updates 
- Explicitly enable EXT_SYNC parameter for Rx/Obs
- Loopback manual sync for each TPL  (we do not combine them yet because
  it requires extra CDC logic)
 2022-02-07 19:14:01 +02:00
Laszlo Nagy b7f34f7bd9 adrv9009zu11eg & common/zcu102 : Fix zynqmp ref clock definition 
The derived clocks of the zynqmp core are not calculated correctly due
rounding issues, instead of 100MHz the value of 99999001 is received
causing warnings during system validation.

This can be fixed/worked around with the proper reference clock
definition.
 2021-08-20 10:46:09 +03:00
Adrian Costina 4cf53f373b Revert "adrv9009zu11eg: Integrate data_offload" 
This reverts commit 78999e154e.
The integration wasn't properly tested
 2021-08-19 21:43:09 +03:00
Istvan Csomortani 78999e154e adrv9009zu11eg: Integrate data_offload 2021-08-06 11:55:24 +03:00
Adrian Costina 7be66b63c1 adrv9009zu11eg:fmcomms8: Fix lane swapping for TX channels 0 and 1 on the FMCOMMS8 2021-02-05 15:07:09 +02:00
Adrian Costina 9364c8501a adrv9009_zu11eg: Add synchronization at application layer 
Switch RX path reset to be controlled by the TPL and use
RX SYSREF as external synchronization for the ADC TPL
Use TX SYSREF for synchornizing the TX DDS
 2020-10-07 09:04:21 +03:00
Adrian Costina c4b94fc564 adrv9009zu11eg: Add S JESD204 parameter for the projects 2020-02-18 11:19:02 +02:00
Adrian Costina d2817863a1 adrv9009zu11eg: Add FMCOMMS8 support 2020-02-18 11:19:02 +02:00
Adrian Costina 29f18e501e adrv9009zu11eg: Cleanup bd file 2020-02-18 11:19:02 +02:00
Adrian Costina 09ad67bfd7 adrv9009zu11eg: Make the project more parametrizable 2019-12-04 14:59:18 +02:00
Adrian Costina 0cb5c0bdaf adv9009zu11eg: Update FPGA to -2. Update DDR4 clock frequency 2019-11-27 16:27:44 +02:00
Adrian Costina dfe3258a4f adrv9009zu11eg: Add axi_sysid 2019-11-19 10:29:57 +02:00
Adrian Costina a589a2c7eb adrv9009_zu11eg_som: Change design partitioning 
Create a structure similar with ADRV936x projects
 2019-11-14 15:25:23 +02:00