9a2d2e8a02
version_upgrade: Update FMCADC4 to 2016.2
2016-09-13 15:04:11 +03:00
236a938425
daq2/a10gx- qsys updates
2016-09-12 14:57:50 -04:00
5df30ac6b0
daq2/a10gx- xcvr sharing
2016-09-12 14:57:50 -04:00
521c41ce32
adrv9371x: Updated a10soc project. Common design differentiates between nios and a10soc carrier
2016-09-08 11:44:45 +03:00
40c9fc92c1
a10soc: Switched to tcl flow
2016-09-08 11:31:06 +03:00
0d095f5da9
a10gx: Added system_type variable in common design
2016-09-08 11:29:14 +03:00
bae63ae5b1
version_upgrade: Update the DAQ3 project to 2016.2
2016-09-06 11:41:37 +03:00
b8c34791d5
version_upgrade: fmcjesdadc1 updated to 2016.2
...
Xilinx IP core JESD204 is updated to version 7.0
2016-09-06 11:41:37 +03:00
b837883b98
pzsdr1/pzsdr1/pzsdr1_cmos_system_constr: Fixed voltage level selection
2016-09-01 17:16:59 +03:00
93fa5aeec3
fmcadc2/vc707: Add adf4355 access, update design to Vivado 2016.2
2016-09-01 16:11:39 +03:00
dc21384002
pzsdr: Update ccpci base design
2016-09-01 09:06:30 +03:00
2f9ac4a342
altera- qsys-script does not support most tcl commands
2016-08-30 11:50:36 -04:00
917da79da1
altera- source defaults for qsys-script
2016-08-30 11:50:36 -04:00
8192e755e1
altera- defaults
2016-08-30 11:50:36 -04:00
1eccf5af07
fmcomms7: Update common design to Vivado 2016.2
2016-08-30 16:46:15 +03:00
2015bcedaa
fmcadc2: Update common design to Vivado 2016.2
2016-08-30 16:42:58 +03:00
6f0d124861
fmcadc5: Update to Vivado 2016.2
2016-08-30 16:09:28 +03:00
4248b9373a
ad6676evb: Update to Vivado 2016.2
2016-08-30 16:08:07 +03:00
a6e6b3f96e
version_upgrade: Update fmcomms1 common design to Vivado 2016.2
2016-08-29 15:59:15 +03:00
2e59f377e1
version_upgrade: Update ac701, mitx045 and zed common design to Vivado 2016.2
2016-08-29 09:50:46 +03:00
271029768c
pzsdr/cmos - swap==1
2016-08-26 10:31:00 -04:00
d18f6aa816
adrv9371x: A10GX, added adcfifo
...
- connected dac dma to 133 MHz clock
- set explicit clock rate to xcvr reference clock bridge
2016-08-26 14:46:48 +03:00
5cc2ab37a5
version_upgrade: Common ZC702 get an upgrade to 2016.2
...
Xilinx IP Clock Wizard updated to version 5.3
2016-08-26 10:20:04 +03:00
cd0c981b50
projects/scripts: Fix to prevent a warning
...
In case of axi_interconnects, when just one slave and master interface is
active, the 'Interconnect Optimization Strategy' is disabled. So this
parameter should be set just if there is more than one slave interface.
2016-08-26 10:08:00 +03:00
6ab137a0e9
projects/scripts: Cosmetics
2016-08-26 10:07:08 +03:00
9dfcfe6146
version_upgrade: adv7511 common script to 2016.2
...
Xilinx IP Clock Wizard updated to version 5.3
2016-08-26 09:52:01 +03:00
264bde77ad
sdrstk- SWAP==1 option
2016-08-24 12:07:13 -04:00
3c6cfdc7b5
adrv9371x: A10GX, switched TX lanes
2016-08-24 18:06:14 +03:00
215edb11c6
adrv9371: A10GX, updated design
...
- disable reconfiguration for RX transceivers and enabled the reconfiguration for TX transceiver. They cannot be enabled at the same time at this point
- update FIFO SIZE to 16 for all DMAs
- updated memory connections to 256 bit and moved clock connection to 133 MHz, for all DMAs.
2016-08-23 18:25:48 +03:00
320f87d63b
sdrstk- fix spi/port connections
2016-08-22 16:52:43 -04:00
270f8a6bbe
adrv9371x: Updated project common
2016-08-22 16:58:21 +03:00
f1b834ab25
scripts: Update script so that all interconnects are optimized for performance
2016-08-22 16:56:02 +03:00
c6b065c349
zc706: Updated DDR3 dacfifo
2016-08-22 16:48:52 +03:00
f697490de6
hdlmake- updates
2016-08-19 15:59:41 -04:00
5c35012f54
sdrstk- updates
2016-08-19 15:59:13 -04:00
8582517712
sdrstk- updates
2016-08-19 15:56:48 -04:00
67bf8f8e78
scripts- fix path and device defaults and override
2016-08-19 15:56:07 -04:00
6ef9555909
sdrstk- added
2016-08-19 13:45:40 -04:00
41203d07e9
adrv9371x: A10GX, update SPI connection
2016-08-18 17:42:27 +03:00
03c83b59bf
adrv9371x/a10soc: Export axi_ad9371_s and xcvr_reconfig_avmm
2016-08-17 19:03:53 +03:00
5d0e08d92e
common/vc707- 2016.2 version
2016-08-17 10:36:19 -04:00
73413366bc
daq2/all - warnings fix
2016-08-17 10:36:00 -04:00
0b6fbf2208
daq2/vc707- 2016.2 updates
2016-08-17 10:34:06 -04:00
ce1fed1ce6
dmafifo- adc/dac split
2016-08-16 12:54:39 -04:00
0694a5015d
kc705- 2016.2 version
2016-08-16 12:54:39 -04:00
8311098384
daq2/kc705- adxcvr changes
2016-08-16 12:54:39 -04:00
8464816c82
dmafifo-split to adc/dac
2016-08-16 12:54:39 -04:00
eb55f600fb
adrv9371x: Initial commit
...
-need to fix dc filter module for AD9371 / altera
2016-08-16 15:50:46 +03:00
5c27ccd1fa
adrv9371x: Added common qsys tcl
2016-08-16 15:34:10 +03:00
4658686ae1
adrv9371x/a10soc: Misc changes for being able to run Linux
2016-08-16 11:56:25 +03:00
39c1c83d00
adrv9371x/a10soc: Fix spi_csn assignment
2016-08-12 10:07:11 +03:00
0b0aa8e6c0
Makefile: Add MMU option to altera makefiles
2016-08-11 17:46:54 +03:00
5d93e542ed
daq2-kcu105: 2016.2 updates
2016-08-11 10:00:41 -04:00
16ad0f4379
kcu105- 2016.2 update
2016-08-11 10:00:41 -04:00
285059aed0
kcu105: Don't use phy reset automation, as it's not supported for KCU105
2016-08-09 10:19:57 +03:00
452d4706d3
kcu105: Update base project to 2015.4.2
...
- change part to revision 1.1 of the board
2016-08-09 10:19:36 +03:00
c6f4def93d
altera- make mmu a make switch
2016-08-08 11:54:51 -04:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
f784557895
lib_refactoring: IOBUF is a Xilinx macro, no need to use with Altera
2016-08-08 15:06:34 +03:00
8f61e11a70
pzsdr: ccpci: Add PCIe reset monitor
...
For reliable and correct operation it is vital that the FPGA is fully
configured and up and running before the PCIe host de-asserts the reset.
Add a small logic circuit that detects de-assertion of the reset signal
that can be used to verify that the reset de-assertion was seen by the
FPGA.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
91782989ad
pzsdr: ccpci: Set IO standard to LVCMOS33 for banks 12 and 13
...
The IO voltage for bank 12 and 13 is 3.3V on the PCIe carrier. Set the
IOSTANDARD of the pins on these banks accordingly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
418217dd10
pzsdr: Remove LED and button signals from PCIe carrier
...
Only the FMC carrier and the breakout board do have push buttons and LEDs.
They are not present on the PCIe carrier. So move the constraints to a
separate file that can be included by the projects that need them and
remove all LED and button related signals from the PCIe project.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
3cff0fa7dc
pzsdr: ccpci: Use PL SPI and GPIO peripherals
...
To be able to access the GPIO pins and the SPI port through the PCIe bridge
we need to use the PL SPI and GPIO controllers rather than the PS
controllers. Adjust the sytem_top.v accordingly so that the PL peripherals
are connected to the external pins.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:29:42 +02:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
ed9e92621c
daq2- spi+xcvr address conflict
2016-08-04 10:50:31 -04:00
999eccc134
daq3: Update A10GX project to Quartus 16.0
2016-08-01 16:19:43 +03:00
9a563de8ff
daq2: A10GX updated project to Quartus 16.0
...
- connected directly axi_ad9680 to xcvr_core, skipping axi_jesd_xcvr
2016-08-01 15:09:53 +03:00
52ae3ddd6c
a10gx: Updated common files to 16.0
2016-08-01 15:08:12 +03:00
7ca8e10004
make: Update Make files
2016-08-01 14:24:48 +03:00
af4c43b6e1
hdl-vivado-2016.2: Update fmcomms2 and pzsdr base design
2016-08-01 13:49:12 +03:00
fbe3d75eb0
cosmetics: Delete trailing whitespace characters
2016-08-01 13:46:46 +03:00
9952a94efb
hdl-vivado-2016.2- ip version updates
2016-07-28 13:44:57 -04:00
6ffe59728b
hdl-vivado-2016.2- update
2016-07-28 13:44:57 -04:00
3b2bde2fa1
hdl-vivado-2016.2- min. addr-space requirement
2016-07-28 13:44:57 -04:00
08f4ba24d5
usb_fx3: Switch PS7 UART to UARTLITE to communicate with the FX3 board
2016-07-28 15:21:38 +03:00
39a5534e00
hdlmake- updates
2016-07-21 16:10:38 -04:00
6df5ba1a7a
daq2- adxcvr version
2016-07-21 16:09:33 -04:00
4532e5c0cb
fmcomms11- support iq mode
2016-07-21 11:58:03 -04:00
c75289be21
fmcomms11- use qpll tx-12g5, cpll rx-6g25
2016-07-19 16:21:49 -04:00
d6243f3d01
update in fmcomms11 tcl and clock constrains
2016-07-18 09:04:13 -04:00
44d9f98e12
adi_project.pl: Fix ADI_NO_BITSTREAM_COMPRESSION detection logic
...
Only enable bitstream compression only if both the
ADI_NO_BITSTREAM_COMPRESSION environment and TCL variable are not set.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-07-14 10:44:42 +02:00
62c7114d77
Enable bitstream compression for Xilinx projects
...
Enabling bitstream compression reduces the size of the generated bitstream.
This means on one hand it will consume less storage, which is especially
useful for the BOOT partition of the ADI images where we store BOOT.BIN
files for all supported platforms.
On the other hand a smaller bitstream is faster to load from the storage
medium and it is also faster to program to the FPGA. So it reduces the
overall boot time as well.
The only downside of bitstream compression is that the bitstream size is no
longer constant, but depends on the actual design and resource utilization.
This will not work with bootloaders that expect a fixed size.
When building a bitstream using the tcl scripts bitstream compression can
be disabled by setting the ADI_NO_BITSTREAM_COMPRESSION environment
variable.
Initial tests show a reduction of a round 50% in size for most ADI
projects.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-07-14 10:16:15 +02:00
12abe2b6b9
fmcomms2: Makefile update
2016-07-12 09:39:24 +03:00
283bf9ad75
fmcomms2_a10GX: Add fmcomms2 on a10gx
2016-07-11 18:37:18 +03:00
e9fe752b7a
fmcomms2_qsys.tcl: Add fmcomms2 block design script for Altera
2016-07-11 18:34:21 +03:00
92c580a84d
daq3: A10GX, updated project to the TCL flow
2016-07-08 12:00:37 +03:00
7be017baa3
daq1: Add AXI PLDDR FIFO to the receive path
...
The AD9684 has two 500 MSPS converter, the system can not handle this
throughput without a FIFO.
2016-07-07 07:15:54 +03:00
9169e20b5e
daq1: Fix the data width on the DMAC interfaces
...
+ HP ports maximum width is 64 bits
+ DMAC's default width is 64, no need for redefinition
2016-07-07 07:15:54 +03:00
48762519b5
make updates
2016-07-06 15:02:00 -04:00
427cc84bb2
axi_ad7616: Rename the physical interface signals to rx_*
...
No functional modification.
2016-07-01 14:45:23 +03:00
69a68a99e0
imageon/zed - remove onboard hdmi and update design
2016-07-01 14:11:49 +03:00
ad491ec04a
updated tcl files after inclusion of ad9162 core
2016-06-30 13:26:16 -04:00
c6c3622816
a10gx: Updated common design adding explicit clock frequency and synchronous reset deassertion
2016-06-30 10:59:29 +03:00
8d558b2538
make: Update Make files
2016-06-29 14:50:07 +03:00
e6494b9a74
axi_ad7616: Change the DMA interface type to Write FIFO
2016-06-29 14:11:02 +03:00
64633e519c
Merge remote-tracking branch 'origin/dev_ad7616' into dev
2016-06-29 12:32:39 +03:00
2e80dec513
adrv9371x/zc706: Update project with the new axi_dacfifo
2016-06-22 12:33:47 +03:00
67c948e821
fmcomms2/a10soc-- bad board design
2016-06-14 12:29:36 -04:00
Istvan Csomortani
Rejeesh Kutty
Adrian Costina
AndreiGrozav
dbogdan
Lars-Peter Clausen
Shrutika Redkar