The extensions have been moved to docs tools.
The source code is available at
https://github.com/analogdevicesinc/doctools
And is installed as before:
(cd docs ; pip install -r requirements.txt --upgrade)
Since the package is listed on the requirements.txt file.
Also, add index for library and projects
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Replaces Symbolator with custom component diagram generator for more
reliable diagrams.
It uses the IP-XACT file, if it is not found, a placeholder is added
instead.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Import aiohttp and asyncio only when needed.
Better warning for unknown signals, params.
Use pattern matching in regmap parsing.
Fixup bundle count.
Add lists clarification to guidelines.
Enforce #1229 rules.
Clean-up Makefile.
Use non-breaking hyphen.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Recommend storing images like any other artifact: in a hierarchical
manner, without "images" subfolders.
This is intended to avoid dangling artifacts when projects are moved,
renamed, or deleted.
Recommend overwriting the page title with a shorter title in the
toctree, so the navigation bar doesn't overflow or get too cluttered.
Add acostina to CODEOWNERS
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Drop part role, use generic adi instead for root adi domain links.
For future reference, the snipped used was:
find ./docs/projects -type f -exec sed -i 's/:part:/:adi:/g' {} \;
Drop Containerfile.
Add option to validate links status (e.g. 200, 404), intended mostly for CI
use to check if a page has disappeared from the internet.
Validate links uses coroutines to launch multiple tasks concurrently,
but do it in bundles to avoid being rate limited.
Fixup regmap styling.
Add imoldovan, jmarques, spop, lbarbosa as docs codeowners.
Remove branch field for links to the hdl repo.
Change git role to display full path.
Fixup ZedBoard link label, remove IP List, add SYSID_ROM dokuwiki link
in ad716_sdz project.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
* Created the first level of pages for the User guide, from Analog Wiki:
* Architecture
* Build HDL
* Customize HDL
* Docs guidelines (edited)
* Git repository
* HDL coding guideline (edited)
* Introduction
* IP cores
* Porting projects (edited)
* Releases
* Third party
* Moved hdl_coding_guideline under user_guide and changed extension to rst
* Deleted hdl_pr_process.md
* docs_guideline: Add reference to project doc template
* porting_project:
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
Add documentation info to the README.md
At adi_hdl_parser.py, filter "_signal_clock" and "_signal_reset"
pseudo buses from component.xml files, append them as description
in the ports table, in the format
"{Bus} [...] is synchronous to this {domain}".
Also, adds collapsible directive
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Moves guidelines to user_guide as docs_guidelines.
Includes Porting HDL project user guide.
Replaces the Excel spreadsheet with raw space divided files.
Includes the 6 pinned at the org.
Contributors shall expand the list as needed.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Sergiu Arpadi
Jorge Marques
Iulia Moldovan
Jorge Marques
Ramon Cristopher Calam