Commit Graph

6 Commits (15ff99a9bdca4745fc494bf02b1134e6f370ab97)

Author SHA1 Message Date
IstvanZsSzekely 74089397b3
util_do_ram: Added keep signal to the FIFO (#1291)
util_do_ram: Added keep signal to the FIFO

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-04-04 14:35:13 +03:00
Iulia Moldovan 68461110aa Replace link in license header from master to main
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2024-01-16 16:48:45 +02:00
Iulia Moldovan 28c06d505f Add/edit copyright and license for .v, .sv files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-11 15:17:41 +03:00
Laszlo Nagy 7a48f1beb9 util_do_ram: Fix Rx path for interrupted transfers
When capture length is not programmed the DMA will interrupt the
transfer once it received all the samples he was set in its descriptor,
this case must be handled by resetting the read process and returning
an end of transfer (eot) to the data offload control logic.
2022-08-04 09:45:52 +03:00
Iulia Moldovan 0c0617d49e libraries: Update modules according to guideline
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Laszlo Nagy 35d32e0143 util_do_ram: Initial version
This IP replaces the ad_mem_asym module as storage element for the data
offload.
Having standard AXIS interface for data will allow
implementation of storages on UltraRAM.
2022-04-28 14:31:32 +03:00