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4 Commits (15ff99a9bdca4745fc494bf02b1134e6f370ab97)

Author SHA1 Message Date
Iulia Moldovan c9a7d4d927 Add copyright and license to .tcl, .ttcl files 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-07-25 15:22:26 +03:00
Bogdan Luncan 72313df81f Updated the makefiles to build the projects in subdirectories based on the build parameters. 
Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.

Note that the 'JESD' and 'LANE' words from the parameter names are stripped.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
 2022-11-14 09:38:42 +02:00
Filip Gherman 1ae375f4fb ad_quadmxfe1_ebz/vcu118: Change drp clock source used for jesd204_phy 
- Added an utility buffer in order to generate the 50Mhz DRP clock.
- 'addn_ui_clockout4' will be used to generate the higher frequency 'sys_mb' clock for Microblaze.

Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
 2022-05-27 00:48:34 +03:00
Laszlo Nagy 1cd866445e ad_quadmxfe1_ebz: Initial version 
Parametrizable project for the QUAD-MxFE platform ADQUADMXFE1EBZ,
ADQUADMXFE2EBZ, ADQUADMXFE3EBZ

Default mode set to:
  TX JESD204C MODE 11, M=16, L=4
  RX JESD204C MODE 4, M=8, L=2

For 204C 64B66B mode as physical layer the Xilinx Phy is uesd.
 2021-11-10 14:03:34 +02:00