68461110aa
Replace link in license header from master to main
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2024-01-16 16:48:45 +02:00
c9a7d4d927
Add copyright and license to .tcl, .ttcl files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
27bb69b44c
Add copyright and license to .sdc files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 10:41:40 +03:00
28c06d505f
Add/edit copyright and license for .v, .sv files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-11 15:17:41 +03:00
34984e67c2
Quartus: Updated to Quartus Standard 22.1 ( #1108 )
2023-04-05 09:36:46 +03:00
db94628cc6
library & projects: Update Makefiles
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-01-27 11:54:05 +02:00
72313df81f
Updated the makefiles to build the projects in subdirectories based on the build parameters.
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Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.
Note that the 'JESD' and 'LANE' words from the parameter names are stripped.
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-11-14 09:38:42 +02:00
1eb5f4985b
projects/common: Add build files templates carriers. Modified Quartus Versions
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The build files are available for the following carriers:
* intel: a10gx, a10soc, c5soc, de10nano, s10soc
* xilinx: coraz7s, kc705, kcu105, vc707, vc709,
vck190, vcu118, vcu128, vmk180,
zc702, zc706, zcu102, zed
* Added Makefiles, system_constr.sdc, system_qsys intel
* Added Makefiles, system_bd, system_constr xilinx
* de10nano, c5soc: Changed quartus version from 20.1.1 to 21.1.0
according to last commit update
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-10-05 10:47:21 +03:00
6b94259a52
projects/common: Add system_top _project templates
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Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Correct code and modify according to guidelines
* Added spacing to ports declaration
* Corrected coding mistakes/misspelling
* Modified/added variables names
* Added seetings (intel) and removed specific optimization settings
* Added assignments to unassigned pins (gpios)
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Correct/Add missing wrapper ports and iobufs
* Added port in wrapper (mainly spi) according to base design file
* Added instances of iobufs where missing
* Corrected gpio assignments or added missing ones
* Corrected minor guidelines mistakes
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
ac701/system_top.v: Change top based on previous projects
* Looked at fmcomms1, fmcomms2 from hdl_2016_r1 and datasheet
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
projects/common: Modify templates to build without errors
* Changed path for adi_env.tcl
* Moved adi_project command before assign intel
* Removed unnecessary spi signals
* Added spi ports with default logic
* a10soc: Removed pl-ddr signals and ports
* ac701: system_bd: Modified mdio interface
system_project: Added adi_board, adiobuf sourcing
system_top: Removed hdmi, i2c, fanpwm, spdif ports
according to base design
* c5soc: Added version settings
Removed unused gpios
* microzed: system_bd: Enabled RTS1 to use FCLK
system_top: Removed hdmi, i2c, unused gpios
* vc709: Separated input from ouput gpio, according to bd
Removed unnecessary ports
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Delete microzed vmk_es templates
* Removed hp0 interconnect from cora base design
* Added extra line to files de10nano
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-09-20 17:00:49 +03:00
bb3027995a
sysid: Add sysid support for de10nano
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make adv7513
make 0540
2022-08-02 14:15:34 +03:00
0d44bfb4dd
axi_hdmi_tx update for: ZedBoard, ZC706, ZC702, de10nano, ADRV9361-Z7035 ( #897 )
2022-03-29 16:51:21 +03:00
fbb2a0e1a0
de10nano: Add hps_conv_usb_n signal to stabilize UART lines
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Without defining this signal, the UART lines receive garbage data
when no cable is connected to the J4 USB UART port.
The GPIO9 is enabled in the reference base design along with the
4MA CURRENT_STRENGTH constraint on the UART pins
2021-01-13 15:36:45 +02:00
e331abedc6
common/de10nano: Cosmetic updates only
2020-12-08 14:38:04 +02:00
8d378c56bf
common/de10nano: Full HD 60 FPS support
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-change the video memory interfacing from f2h_axi_slave to
f2h_sdram0
- add f2h_sdram1 port as the default interface for converter DMA
- set as default the full HD resolution at 60 FPS (pixel clock 148.5MHz)
- use a second 200MHz(198MHz) clock from the pixel_clk_pll, as DMA source
to destination clock.
2020-12-08 14:38:04 +02:00
c048a9243a
de10nano: Fix IO assignments
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- define IO assignments for HPS SPI master
- delete unused GPIO ports
2020-10-30 10:55:01 +02:00
043ddbaf9f
cn0540: Add de10nano reference design
2020-09-15 18:14:23 +03:00
fd1c3c7cdd
common/de10nano: Add de10nano base design
2020-09-15 18:14:23 +03:00
Iulia Moldovan
ladace
Bogdan Luncan
laurent-19
Sergiu Arpadi
PopPaul2021
Adrian Costina
AndreiGrozav
Istvan Csomortani
Stanca Pop
Stanca.Pop