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6536 Commits (15ff99a9bdca4745fc494bf02b1134e6f370ab97)

Author SHA1 Message Date
Sergiu Arpadi cf3bd8528d spi_engine_offload: Update hw.tcl 
Define trigger input signal as if_pwm interface type. This ensures
compatibility with axi_pwm_gen pwm outputs.
 2023-03-30 14:55:59 +03:00
Sergiu Arpadi 369e34425f axi_pwm_gen: Update timing constraints, hw.tcl and sdc files. 
Not using util_cdc_constr.tcl
 2023-03-30 14:55:59 +03:00
alin724 7da9827782 ad7606x_fmc: Fix up_cpack2 module's SAMPLE_DATA_WIDTH parameter 2023-03-29 21:33:33 +03:00
alin724 f945520020 axi_ad7606x: Fix data width and order of ADC channels 2023-03-29 21:33:33 +03:00
AndreiGrozav e883f6ecd6 adi_xilinx_device_info_enc: Enlarge detection 
Add detection scenario for xazu*, xczu*, xqzu* and ultrascale+ packages.
 2023-03-29 16:44:25 +03:00
laurent-19 2ae09c9808 Check guidelines. Remove redundancies 
* Removed empty/commented lines
 * Regenerated Makefiles
 * Removed redundancies adc channels data width
 * Set data width 32-bit: max resolution and CRC header

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 2023-03-29 15:08:07 +03:00
laurent-19 1bef2bf304 projects/ad7134_fmc: Update bd SPIE hierarchy, spi trigger, ODR 
* Updated bd spi hierarchy, see library/spi_engine.tcl
 * Enabled ext_clk for PWM to use 96 MHz spi clk
 * Modified PWM channels used:
  - ch1: ODR - 850 ns period, 130 ns high time
	 ==> max fODR = 1.18 MHz
  - ch0: trigger - 850 ns period, 30 phase shift
         ==> 10 ns between falling ODR rising DCLK
 * Changed spi offload trigger signal:
  - replaced edge detect,sync_bits IPs with PWM trigger

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 2023-03-29 15:08:07 +03:00
laurent-19 553774319a projects/cn0561: Update design: spi trigger, ODR, spi hierch 
* Enabled ext_clk for PWM to use 96 MHz spi clk
 * Modified PWM channels used:
  - ch1: ODR - 850 ns period, 130 ns high time
	 ==> max fODR = 1.18 MHz
  - ch0: trigger - 850 ns period, 30 phase shift
         ==> 10 ns between falling ODR rising DCLK
 * Changed spi offload trigger signal:
  - replaced edge detect,sync_bits IPs with PWM trigger
 * Updated bd SPIE hierarchy, see library/spi_engine.tcl

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 2023-03-29 15:08:07 +03:00
Stanca Pop ee30c64923 projects/ad4134_fmc: Initial commit add support 
* Updated reference design: spi trigger, ODR parameters
  - enabled ext_clk for PWM to use 96 MHz spi clk
  - mofified PWM channels used:
  - ch1: ODR - 850 ns period, 130 ns high time
	 ==> max fODR = 1.18 MHz
  - ch0: trigger - 850 ns period, 30 phase shift
         ==> 10 ns between falling ODR rising DCLK
  - spi offload trigger signal: PWM trigger used
 * Moved mem_interconnect to hp1
 * Added dclkio GPIO
 * Updated bd SPIE hierarchy, see library/spi_engine.tcl

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 2023-03-29 15:08:07 +03:00
Sergiu Arpadi 445cca61ef SPI Engine: Update spi_engine.tcl 
The SPI Engine cores were named directly inside the script and this
would mean that for multiple SPI Engine instances IPs with the same
name would appear. These updates will introduce the hierarchy name
into the name given to the cores and will therefore allow for
multiple instances of SPI Engine to be added to the same Xilinx
project.

Projects which use spi_engine.tcl will be updated to account for
these changes.
 2023-03-29 15:08:07 +03:00
Paul Pop 890569d53f projects/cn0579/de10nano: Fix Critical Warnings 
- Quartus version was updated
- the start_n output port was deteled from system_top.v
- the ""mixed_port_feed_through_mode" parameter of RAM can not have value "old"" warning was disabled
- update Makefile copyright year

Signed-off-by: Paul Pop <paul.pop@analog.com>
 2023-03-24 09:09:15 +02:00
laurent-19 83284107a2 library/axi_pwm_gen: Assign correct reg value to offset_0 
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 2023-03-22 17:58:18 +02:00
Jem Geronimo 75adcb4e37
adi_project_intel.tcl: bugfix for ad_project_dir (#1101) 
bug:
  say "make LVDS_CMOS_N=0"
  - will set ad_project_dir as LVDSCMOSN0
  - will then set system_qip_file as LVDSCMOSN0/system_bd/synthesis/system_bd.qip
  - build error reveals system_bd can't be found
  - maybe due to setting ad_project_dir as a relative file path
fix:
  - set ad_project_dir as an absolute file path

Signed-off-by: Jem Geronimo <Johnerasmusmari.Geronimo@analog.com>
 2023-03-17 19:09:33 +08:00
Paul Pop b84d50bbb3 projects/cn0579: Initial commit for Coraz7s and DE10Nano 2023-03-16 16:20:44 +02:00
Iulia Moldovan bd46fdc3e8 check_guideline.py: Add execute permissions 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-03-15 17:47:46 +02:00
PopPaul2021 41f4f1a988 docs/regmap: Updates on regmap text files to match the Wiki page updates. 2023-03-14 10:08:03 +02:00
Iulia Moldovan 9977df074b vmk180_system_bd.tcl: Fix issue with PMC_I2C_PERIPHERAL 
* Issue appeared when updating to Vivado 2022.2

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-03-09 09:53:41 +02:00
Iulia Moldovan 95e63deaff adi_env.tcl: Update Vivado version to 2022.2 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-03-09 09:53:41 +02:00
alin724 341ade7ae0 ad7606x: Fix system_top module's gpio instances and add missing adc_serpar,_refsel pins 2023-03-08 13:06:03 +02:00
PopPaul2021 e94df1d7da library/axi_ad7768: Data valid signal updates 
If the sampling clock is lower than dclk*number_of_active_lines*32 the interface should wait for the next adc_ready signal to reset the counter.
The adc_valid_p signal should be set high just for a clock period after the sample was captured.
 2023-03-01 15:52:05 +02:00
PopPaul2021 2f7c8edef0 projects/*/a10gx: Support for A10GX carrier is discontinued. 2023-03-01 14:55:18 +02:00
Istvan-Zsolt Szekely 72461b2218 adi_board.tcl: Support multiple common channels connections between different TX adxcvr's and util_xcvr 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
 2023-02-09 17:08:18 +02:00
Jem Geronimo 2db944396f
axi_pwm_gen: add: intel support (#1080) 
Signed-off-by: Jem Geronimo <johnerasmusmari.geronimo@analog.com>
 2023-02-07 18:27:04 +08:00
AndrDragomir a8a01aaaf4 projects/adrv9009zu11eg: Fix lane swap on tx1_c when used with fmcomms8 2023-02-03 11:00:33 +02:00
Istvan-Zsolt Szekely 15e9c65c83 library/common/util_pulse_gen: Fix for unupdateable registers 
- Fixed an issue where if Pulse Period is set to 0, the load_config won't work

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
 2023-02-02 11:33:08 +02:00
Iulia Moldovan db94628cc6 library & projects: Update Makefiles 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-01-27 11:54:05 +02:00
LIacob106 e932e6f4f8 projects/adrv9009zu11eg: JESD support for fmcomms8 
for configurations 4, 8 TX_L and 4 RX/ORX_L

Signed-off-by: LIacob106 <liviu.iacob@analog.com>
 2023-01-26 15:38:38 +02:00
LIacob106 261c0d1b90 projects/adrv9009zu11eg: JESD support for adrv2crr_fmc 
for configurations 2, 4 TX_L and 2 RX/ORX_L

Signed-off-by: LIacob106 <liviu.iacob@analog.com>
 2023-01-26 15:38:38 +02:00
LIacob106 9b8604b9a2 adrv9009/zc706: Add clkgen div to match the desired freq 2023-01-26 15:36:45 +02:00
LIacob106 911b8bbc99 projects/adrv9009: JESD support for 1, 2 TX_L and 1 RX/ORX_L 
Signed-off-by: LIacob106 <liviu.iacob@analog.com>
 2023-01-26 15:36:45 +02:00
LIacob106 10a87f34d3 projects/fmcomms8: Interconnect m_axi port for rx_xcvr 
Signed-off-by: LIacob106 <liviu.iacob@analog.com>
 2023-01-26 15:35:12 +02:00
Iulia Moldovan a88215abc1 axi_adrv9001/intel: Add dummy parameter IODELAY_ENABLE in adrv9001_rx 
- Issue introduced by commit 173f4a83d4
 - When IODELAY_ENABLE was inserted in axi_adrv9001_if for adrv9001_rx (Xilinx instance),
   for Intel instance (intel/adrv9001_rx.v) was omitted and caused a build error for
   adrv9001/a10soc

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-01-18 14:52:30 +02:00
Filip Gherman 4c1f68b119 vcu118_system_bd.tcl: Additional microblaze interrupt for VCU118 2023-01-17 13:31:16 +02:00
alin724 189624a655 ad7606x_fmc: Initial commit 2023-01-12 17:38:14 +02:00
alin724 cd448ea0d0 axi_ad7606x: Initial commit 2023-01-12 17:38:14 +02:00
AndreiGrozav 22fbb05256 Update IPs based on up_adc_common changes 2023-01-12 13:09:35 +02:00
alin724 8ad959c16f up_adc_common: Update custom RD/WR mechanism 2023-01-12 13:09:35 +02:00
Filip Gherman 4257a47b7a intel/adi_jesd204: Enable master clock generation block for S10 H-Tile 2023-01-10 13:07:04 +02:00
LIacob106 19249b51db projects/fmcomms8: JESD support for 2, 4 TX_L and RX/ORX_L 
On zcu102 carrier.

Signed-off-by: LIacob106 <liviu.iacob@analog.com>
 2023-01-10 13:06:23 +02:00
Iulia Moldovan 45346b1957 library: Cosmetic changes for modules that use ad_serdes_* 
Edited in:
 * axi_ad9122
 * axi_ad9434
 * axi_ad9684
 * axi_ad9739a
 * axi_ad9783
 * axi_adrv9001
 * ad_serdes_clk
 * ad_serdes_in
 * ad_serdes_out

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2022-12-15 14:22:40 +02:00
Iulia Moldovan 173f4a83d4 ad_serdes: Add features and update their instances in /library 
- ad_serdes_in:
  * Removed unused ports: loaden, phase, locked
  * Added IODELAY_ENABLE is set to be by default 1
  * Added conditional instantiation (using IODELAY_ENABLE) to IDELAY modules
  * Added conditional instantiation (using IODELAY_CTRL_ENABLED) to IDELAYCTRL module, based on IODELAY_ENABLE

- library: Update ad_serdes_in instances: add IODELAY_ENABLE
   * Edited in:
     * axi_ad9434
     * axi_ad9684
     * axi_adrv9001

- ad_serdes_out:
  * Removed unused port: loaden

- library: Update ad_serdes_out instances
   * Edited in:
     * axi_ad9122
     * axi_ad9739a
     * axi_ad9783
     * axi_adrv9001

- ad_serdes_clk:
  * Remove unused ports: loaden, phase

- library: Update ad_serdes_clk instances
   * Edited in:
     * axi_ad9122
     * axi_ad9434
     * axi_ad9684

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2022-12-15 14:22:40 +02:00
sergiu arpadi 1b1cbfc8ef ad4110: Initial commit 2022-12-14 15:01:16 +02:00
Ionut Podgoreanu b3f3f7c392 docs/regmap: Added the regmap file for the generic TDD controller 2022-12-13 16:26:02 +02:00
Ionut Podgoreanu a3e1e6286b ad9081_fmca_ebz_x_band: Integrate the new TDD in project 2022-12-13 16:26:02 +02:00
Ionut Podgoreanu 5b95b6ce1f ad9081_fmca_ebz: Integrate the new TDD in project 2022-12-13 16:26:02 +02:00
Ionut Podgoreanu ef278e1c88 library/axi_tdd: Add generic TDD engine 
Replaced the existing axi_tdd with the new version
* Added DEFAULT_POLARITY synth parameter and RO register
* Added TDD_STATUS register
* Added TDD_SYNC_RST feature
* Used the asy_ prefix for signals which are not synced
* Added logic to force the state from ARMED to RUNNING when startup_delay=0
* Added feature to finish the burst when the module is disabled before its completion

Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
 2022-12-13 16:26:02 +02:00
Ionut Podgoreanu 7faefab1be library/scripts: Add SV support for Intel boards 
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
 2022-12-13 16:26:02 +02:00
AndrDragomir 8b9175a80c projects: Fix intermitent timing violation on a10soc 
adrv9009, dac_fmc_ebz, ad9081_fmca_ebz, fmcomms8:
Increased PLACEMENT_EFFORT_MULTIPLIER global parameter to 1.2 for increased quality of placement
 2022-12-13 14:21:24 +02:00
Sergiu Arpadi f64830364c ad469x: Use axi_pwm_gen; clean-up 
Replace axi_pulse_gen with axi_pmw_gen for softare support
considerations. Remove common/config.tcl and update project scripts
accordingly.
 2022-11-18 12:54:45 +02:00
PopPaul2021 eb663876d7 axi_ad7768: modified adc_format values and crc_err flag has to be RW1C 2022-11-15 15:43:46 +02:00