7ec4c00f9f
axi_ad7616: DMA is always ready
2016-04-29 16:36:33 +03:00
427f85959c
axi_ad7616: Fix the AXI stream interface
2016-04-29 16:34:34 +03:00
33199263e1
axi_ad7616: Delete burst_length register
...
This was an unnecessary feature of the hdl core.
2016-04-29 16:28:48 +03:00
d5d7c12f0e
axi_ad7616: Fix the register map
2016-04-25 11:36:39 +03:00
2ccdd426ec
axi_ad7616: Fix the rd_db_valid generation and do some cosmetic changes.
2016-04-25 11:28:22 +03:00
665bfbc991
axi_ad7616: Add M_AXIS_READY_ENABLE parameter
...
m_axis_ready can be driven by the DMA or can have a constant active state. By default is always one.
2016-03-15 18:38:55 +02:00
573146aa96
axi_ad7616: Fix the data width of the AXI stream interface
2016-03-10 16:38:53 +02:00
3d3d1098b4
axi_ad7616: Default DATA_WIDTH is 8 bits
2016-01-28 16:02:01 +02:00
122667259f
ad7616_sdz: Update Make file
2016-01-28 14:48:44 +02:00
fbb0d368bf
axi_ad7616: Add support for parallel interface
2016-01-28 12:37:22 +02:00
cd43ebd8bc
axi_ad7616: The OP_MODE parameter is no longer required
2016-01-26 11:05:33 +02:00
2a17ce275c
axi_ad7616: Control inputs are controlled through GPIO
...
The following control inputs are controlled through GPIO: reset_n, seq_en, hw_rngsel, chsel, crcen, burst and os.
2016-01-25 17:50:50 +02:00
c29dd8fad5
axi_ad7616: Fix Makefile
2015-12-21 19:39:58 +02:00
0b55325db9
axi_ad7616: Fix IP packaging script
2015-12-21 19:39:14 +02:00
17e7d1b86f
ad7616: Add Makefiles
2015-12-21 17:09:42 +02:00
8ae9de8fba
axi_ad7616: Update core
...
+ Both the data width and number of SDI lines are configurable
+ SER1W line is hardware configurable, it was removed from the IP
+ Add 'Hardware mode' support for the controller
2015-12-14 16:00:56 +02:00
d6eae81bc1
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 18:14:21 +02:00
952a491f59
axi_ad7616: Add spi engine to the core
2015-11-12 16:12:16 +02:00
64d1948ea0
axi_ad7616: Initial commit
2015-11-10 13:32:56 +02:00
Istvan Csomortani
Dragos Bogdan